SBAA548A April   2022  – May 2022 ADS8588S , ADS8681 , ADS8686S , ADS8688 , ADS8688A

 

  1.   Abstract
  2.   Trademarks
  3. 1Introduction
  4. 2Circuit Design and Test System
    1. 2.1 Design Description
      1. 2.1.1 Input Protection
      2. 2.1.2 Power Supply Design and Protection
      3. 2.1.3 Digital Isolation Design
      4. 2.1.4 Component Selection and Layout Considerations
    2. 2.2 Test System
      1. 2.2.1 Reference
    3. 2.3 Standards and Test Criteria
  5. 3Test Details and Results
    1. 3.1 Electrical Fast Transients (EFT)
    2. 3.2 Electrostatic Discharge (ESD)
    3. 3.3 Surge Immunity (SI)
    4. 3.4 Conducted Immunity (CI)
    5. 3.5 Radiated Immunity (RI)
    6. 3.6 Radiated Emissions (RE)
      1.      20
  6. 4Schematics
  7. 5PCB Layouts
  8. 6Bill of Materials
  9. 7Acknowledgments
  10. 8References
  11. 9Revision History

Electrical Fast Transients (EFT)

The IEC 61000-4-4 standard specifies the details about the EFT test in terms of the test signals and the requirements. The purpose of the test is to verify the EFT immunity to burst stream of transient signals with short duration and fast rise time that can couple into the signal line. The standard defines four test voltage levels with two repetition frequencies for signal and control ports; 0.25 kV, 0.5 kV, 1 kV, and 2 kV at 5-kHz and 100-kHz repetition frequency. Each test covers positive and negative polarity discharge. The ADS8686S EMC test board was tested with the standard 1 kV and 2 kV, and also was tested at 4-kV levels, which are higher than required, but sometimes requested. The 100-kHz repetition frequency EFT testing is less commonly requested and more aggressive than 5 kHz. The ADS8686S EMC test board was tested at both frequencies. The EFT transient burst consists of 75 fast pulses followed by a break interval, and the burst stream is defined and tested as 15 ms for 5 kHz and 0.75 ms for 100 kHz with bursts repeated every 300 ms. Each individual burst pulse is a double exponential waveform with a rise time of 5 ns and a total pulse duration of 50 ns. The total test time for each test is approximately one minute.

Figure 3-1 shows the diagram of the setup and connection for the EFT immunity test. In this setup, the EFT threat is applied to the analog input of the ADS8686S EMC test board by running 2 m of twisted pair input wires through a 1-m length standard capacitive EFT clamp. All the cables in the test setup are kept in the insulation support. The EUT is placed on top of a ground reference plane (GRP) and isolated from the GRP by an insulating support material in 0.1-m height.

Figure 3-1 Diagram of Laboratory Setup for EFT Test

Figure 3-2 shows a photograph of the actual setup for the EFT test.

GUID-20220322-SS0I-K1FZ-L2GP-XSHKKBS7DK4Z-low.jpg Figure 3-2 Photograph of Laboratory Setup for EFT Test

Table 3-1 shows the results of the EFT test.

Table 3-1 EFT Test Result
Test IEC Standard Test Signal Test Level Criterion Test Result
Voltage Frequency

EFT

IEC 61000-4-4

±1 kV

5 kHz

2

A

Pass

±2 kV

3

B

Pass

±4 kV

4

B

Pass

±1 kV

100 kHz

2

A

Pass

±2 kV

3

B

Pass

±4 kV

4

B

Pass