SBAA583 july   2023 PCM1820 , PCM1820-Q1 , PCM1821 , PCM1821-Q1 , PCM1822 , PCM1822-Q1 , PCM3120-Q1 , PCM5120-Q1 , PCM6120-Q1 , TLV320ADC3120 , TLV320ADC5120 , TLV320ADC6120

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1Introduction
    1. 1.1 AC Coupled Systems
    2. 1.2 DC Coupled System
  5. 2AC Coupling Schemes
    1. 2.1 Equivalent Circuit
    2. 2.2 Input Pin Waveforms with AC Coupling
    3. 2.3 Selection of Coupling Capacitor
    4. 2.4 Quick Charge Circuit
    5. 2.5 Selection of Capacitor Type
    6. 2.6 Single-Ended and Differential Mode
    7. 2.7 S.N.R in AC Coupled Circuits
  6. 3DC Coupled Scheme
    1. 3.1 Biasing the Pins
    2. 3.2 Electrical Characteristics
    3. 3.3 Application Circuits
      1. 3.3.1 S.N.R in DC Coupled Circuits
  7. 4Application Examples
    1. 4.1  Electret Condenser Microphone: Single Ended DC- Coupled Input
    2. 4.2  Electret Condenser Microphone: Single Ended AC Coupled Input
    3. 4.3  Selection of a Microphone
    4. 4.4  Condenser Microphone: Differential DC-Coupled Input
    5. 4.5  Condenser Microphone: Differential AC-Coupled Input
    6. 4.6  MEMS Microphone: Differential AC Coupled Input
    7. 4.7  Circuit With No Offset and Response Down to DC
    8. 4.8  Improving SNR by Summing the Output of 2 ADC Channels
    9. 4.9  Measure a High Voltage Waveform (+-50 V)
    10. 4.10 I2C Listing
  8. 5Summary
  9. 6References

3.3 Application Circuits

For a single-ended input, the static DC bias at the input pin VIN must remain between 0 and Vref. An optimum static DC bias for the input pin is Vref/2. For a Vref of 2.75 V, the bias level is 1.375 V enabling a 1-Vrms signal to be coupled to the ADC.

The static DC bias of 1.375 V appears as a DC offset at the output of the ADC. Selection of the digital high-pass filter removes the DC offset from the digital data.

The static DC bias is amplified by setting a PGA gain.

GUID-20230501-SS0I-6S7D-FKG8-RJWVKKFLZZP5-low.svgFigure 3-12 Single-Ended DC Coupled Waveform
GUID-20230501-SS0I-DHGC-TDM3-LGWSDZNS5JSV-low.svgFigure 3-13 Single-Ended DC Coupled Circuit

For a differential input, the VIN and INV_VIN Signals can have a static DC bias between 0 and AVDD. An optimum static bias is Vref/2 for both VIN and INV_VIN signals. With a Vref of 2.75 V, the optimum static bias is 1.375 V which supports a differential 2-Vrms signal to be coupled to the ADC.

GUID-20230501-SS0I-HXTN-GBBS-XRMSBHVLXBB0-low.svgFigure 3-14 Differential DC Coupled Signal
GUID-20230501-SS0I-WRP5-K1BR-9CLL6QPJTH0V-low.svgFigure 3-15 Differential DC Coupled Circuit

If VIN and INV_VIN have the same static DC bias, then no DC offset exists at the output of the ADC.

The waveforms at VIN and INV_VIN are 180 degrees out of phase with each other.

Table 3-2 lists input signal levels that correspond to full scale digital value.

Table 3-2 Input Signal Levels
AVDD (V)VREF/2 (V)Vrms
Single Ended (V) Differential (V)
3.31.37512
1.80.68750.51