SBOU315 March   2024 PGA849

 

  1.   1
  2.   Description
  3.   Features
  4.   Applications
  5.   5
  6. 1Evaluation Module Overview
    1. 1.1 Introduction
    2. 1.2 Kit Contents
    3. 1.3 Specification
    4. 1.4 Device Information
  7. 2Hardware
    1. 2.1 EVM Circuit Description
    2. 2.2 Jumper Settings
    3. 2.3 Power-Supply Connections
    4. 2.4 Analog Input and Output Connections
    5. 2.5 Reference Input
    6. 2.6 Digital Input Pins and Gain Control
    7. 2.7 Modifications
    8. 2.8 Best Practices
      1. 2.8.1 Electrostatic Discharge Caution
      2. 2.8.2 Hot Surface Warning
  8. 3Hardware Design Files
    1. 3.1 Schematic
    2. 3.2 PCB Layout
    3. 3.3 Bill of Materials
  9. 4Additional Information
    1. 4.1 Trademarks
  10. 5Related Documentation

2.6 Digital Input Pins and Gain Control

The PGA849 provides eight binary gain settings, from an attenuating gain of 0.125V/V to a maximum of 16V/V. The gain is controlled by three digital selection pins: A0, A1, and A2. By default, the PGA849 is configured to a gain of 0.125V/V.

The evaluation board provides shunt jumpers J10, J11, and J12 to set the PGA849 gain-control selection pins. Table 3-4 lists the gain-control options. To set the gain-control pin high, install the shunt on the corresponding jumper. To set the gain-control pin low, remove the shunt jumper.

Table 2-4 PGA849EVM Gain Control

A2

Jumper J10

Connector J15.1

A1

Jumper J11

Connector J15.2

A0

Jumper J12

Connector J15.3

PGA Gain (V/V)
Low (Open) Low (Open) Low (Open) 0.125
Low (Open) Low (Open) High (Shunt) 0.25
Low (Open) High (Shunt) Low (Open) 0.5
Low (Open)

High (Shunt)

 High (Shunt) 1
High (Shunt)

Low (Open)

 Low (Open) 2
High (Shunt) Low (Open) High (Shunt) 4
High (Shunt)

High (Shunt)

 Low (Open) 8
High (Shunt) High (Shunt) High (Shunt) 16

Alternatively, the A0, A1, and A2 digital pins can be driven externally through connector J15. Any pin that is not driven by an external source, or any shunt that is left open, is biased at DGND using pulldown resistors. Figure 3-6 shows the gain-setting block diagram.

GUID-20240311-SS0I-NPW8-PGSC-4WC2ZGXB22W4-low.svgFigure 2-6 PGA849EVM Gain Control