SDAA081 September   2025 DP83825I

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1Introduction
  5. 2Troubleshooting the Application
    1. 2.1 Schematic Checklist
    2. 2.2 Device Health Checks
      1. 2.2.1 Voltage Checks
      2. 2.2.2 Probe the RESET_N Signal
      3. 2.2.3 Probe RBIAS
      4. 2.2.4 Probe the XI Clock
      5. 2.2.5 Probe the Strap Pins During Initialization
      6. 2.2.6 Probe the Serial Management Interface (MDC, MDIO)
        1. 2.2.6.1 Read and Check Register Values
    3. 2.3 MDI Health Checks
      1. 2.3.1 Magnetics
      2. 2.3.2 Probe the MDI Signals
      3. 2.3.3 Check the Link Quality
      4. 2.3.4 Compliance
    4. 2.4 RMII Health Check
    5. 2.5 Loopback and PRBS
      1. 2.5.1 Loopback Modes
      2. 2.5.2 Transmitting and Receiving Packets with the MAC
      3. 2.5.3 Transmitting and Receiving Packets with BIST
  6. 3Summary
  7. 4References

2.2.4 Probe the XI Clock

The following guidelines are the main specifications to reference for compatible input clocks:

Table 2-2 25MHz Crystal Specifications
Parameter Min Typ Max Unit
Frequency 25 MHz
Frequency Tolerance -50 50 ppm
Load Capacitance 15 40 pF
ESR 50 Ω

Probing on the crystal nodes can change the capacitive loading and therefore change the operational frequency.

Table 2-3 Oscillator Specifications
Parameter Min Typ Max Unit
Frequency

25 (RMII Leader)

50 (RMII Follower)

 MHz
Frequency Tolerance -50 50 ppm
Rise or Fall Time 5 ns
Duty Cycle 40 60 %

The amplitude of the oscillator must be a nominal voltage of VDDIO.

Note: For more information on designing with a crystal network, please refer to the Selection and specification of crystals for Texas Instruments Ethernet physical layer transceivers, application note.