SFFS083 June   2021 TLIN2022A-Q1

 

  1.   Trademarks
  2. 1Overview
  3. 2Functional Safety Failure In Time (FIT) Rates
  4. 3Failure Mode Distribution (FMD)
  5. 4Pin Failure Mode Analysis (Pin FMA)

4 Pin Failure Mode Analysis (Pin FMA)

This section provides a Failure Mode Analysis (FMA) for the pins of the TLIN2022A-Q1. The failure modes covered in this document include the typical pin-by-pin failure scenarios:

  • Pin short-circuited to Ground (see Table 4-2)
  • Pin open-circuited (see Table 4-3)
  • Pin short-circuited to an adjacent pin (see Table 4-4)
  • Pin short-circuited to supply (see Table 4-5)

Table 4-2 through Table 4-5 also indicate how these pin conditions can affect the device as per the failure effects classification in Table 4-1.

Table 4-1 TI Classification of Failure Effects
ClassFailure Effects
APotential device damage that affects functionality
BNo device damage, but loss of functionality
CNo device damage, but performance degradation
DNo device damage, no impact to functionality or performance

Figure 4-1 shows the device pin diagram. For a detailed description of the device pins, please refer to the Pin Configuration and Functions section in the TLIN2022A-Q1 data sheet.

Figure 4-1 DRB Pin Diagram
Figure 4-2 D Pin Diagram

Following are the assumptions of use and the device configuration assumed for the pin FMA in this section:

  • All conditions within the recommended operating conditions
Table 4-2 Pin FMA for Device Pins Short-Circuited to Ground
Pin Name Pin No. Description of Potential Failure Effect(s) Failure Effect Class
RXD1 1 RXD1 biased dominant, no communication from LIN1 bus to MCU possible. B
EN1 2 LIN1 channel may only operate in standby mode after power on. If short on EN1 occurs in normal mode, LIN1 channel would be forced to enter sleep mode and could disable LIN communication. B
TXD1 3 TXD1 biased dominant, no communication from MCU to LIN1 bus possible. B
RXD2 4 RXD2 biased dominant, no communication from LIN2 bus to MCU possible. B
EN2 5 LIN2 channel may only operate in standby mode after power on. If short on EN2 occurs in normal mode, LIN2 channel would be forced to enter sleep mode and could disable LIN communication. B
NC 6 No impact to performance. D
TXD2 7 TXD2 biased dominant, no communication from MCU to LIN2 bus possible. B
GND 8 None D
LIN2 9 LIN2 biased dominant, no LIN communication possible. B
VSUP 10 Device is unpowered and will not function. B
NC 11 No impact to performance. D
NC 12 No impact to performance. D
LIN1 13 LIN1 biased dominant, no LIN1 communication possible. B
NC 14 No impact to performance. D
Note: DMT package includes a thermal pad
Table 4-3 Pin FMA for Device Pins Open-Circuited
Pin Name Pin No. Description of Potential Failure Effect(s) Failure Effect Class
RXD1 1 No communication from LIN1 bus to MCU possible. B
EN1 2 Biased low due to internal pull-down so LIN1 in standby mode. B
TXD1 3 No communication from MCU to LIN1 bus possible. B
RXD2 4 No communication from LIN2 bus to MCU possible. B
EN2 5 Biased low due to internal pull-down so LIN2 in standby mode. B
NC 6 No impact to performance. D
TXD2 7 No communication from MCU to LIN2 bus possible. B
GND 8 Device is unpowered and will not function. B
LIN2 9 No LIN2 communication possible. B
VSUP 10 Device is unpowered and will not function. B
NC 11 No impact to performance. D
NC 12 No impact to performance. D
LIN1 13 No LIN1 communication possible. B
NC 14 No impact to performance. D
Note: DMT package includes a thermal pad
Table 4-4 Pin FMA for Device Pins Short-Circuited to Adjacent Pin
Pin Name Pin No. Shorted to Description of Potential Failure Effect(s) Failure Effect Class
RXD1 1 EN1 LIN1 will go into sleep mode when a dominant bit is received on the LIN1 bus, disabling communication. B
EN1 2 TXD1 With TXD toggling, LIN1 channel will transition between normal and sleep mode, corrupting communication. B
TXD1 3 RXD2 Communication on TXD1 will corrupt the received data from LIN2 to RXD2. B
RXD2 4 EN2 With data toggling on RXD2 via LIN2 bus, EN2 toggles and causes LIN2 channel to transition between normal and sleep modes. B
EN2 6 NC No impact to performance. D
NC 7 TXD2 No impact to performance. D
GND2 8 LIN2 LIN2 biased dominant, no LIN1 communication possible. B
LIN2 9 VSUP LIN2 biased recessive, no LIN2 communication possible. B
VSUP 10 NC No impact to performance. D
NC 11 NC No impact to performance. D
NC 12 LIN1 No impact to performance. D
LIN1 13 NC No impact to performance. D
Note: The DMT package includes a thermal pad. There is a chance the thermal pad is soldered down and could short to any pin on device. What the thermal pad is soldered to determines the behavior. Example: if soldered to a ground plane then the adjacent pins would behave as if shorted to ground.
Table 4-5 Pin FMA for Device Pins Short-Circuited to VSUP supply
Pin Name Pin No. Description of Potential Failure Effect(s) Failure Effect Class
RXD1 1 Absolute maximum voltage violation, transceiver may be damaged. A
EN1 2 Absolute maximum voltage violation, transceiver may be damaged. A
TXD1 3 Absolute maximum voltage violation, transceiver may be damaged. A
RXD2 4 Absolute maximum voltage violation, transceiver may be damaged. A
EN2 5 Absolute maximum voltage violation, transceiver may be damaged. A
NC 6 No impact to performance. D
TXD2 7 Absolute maximum voltage violation, transceiver may be damaged. A
GND 8 Device is unpowered and will not function. B
LIN2 9 LIN2 biased recessive, no LIN2 communication possible. B
VSUP 10 None D
NC 11 No impact to performance. D
NC 12 No impact to performance. D
LIN1 13 LIN1 biased recessive, no LIN1 communication possible. B
NC 14 No impact to performance. D
Note: DMT package includes a thermal pad