SFFS182 June   2021 LM5146

 

  1.   Trademarks
  2. 1Overview
  3. 2Failure Mode Distribution (FMD)
  4. 3Functional Safety Failure In Time (FIT) Rates
  5. 4Pin Failure Mode Analysis (Pin FMA)

2 Failure Mode Distribution (FMD)

The failure mode distribution estimation for LM5146 in Table 2-1 comes from the combination of common failure modes listed in standards such as IEC 61508 and ISO 26262, the ratio of sub-circuit function size and complexity and from best engineering judgment.

The failure modes listed in this section reflect random failure events and do not include failures due to misuse or overstress.

Table 2-1 Die Failure Modes and Distribution
Die Failure ModesFailure Mode Distribution (%)
HO or LO gate driver stuck off20%
HO or LO output not in specification – voltage or timing45%
Ho or LO gate driver open – high Z10%
HO or LO gate driver stuck on20%
PGOOD false trip, fails to trip5%

The FMD in excludes short circuit faults across the isolation barrier. Faults for short circuit across the isolation barrier can be excluded according to ISO 61800-5-2:2016 if the following requirements are fulfilled:

  1. The signal isolation component is OVC III according to IEC 61800-5-1. If a SELV/PELV power supply is used, pollution degree 2/OVC II applies. All requirements of IEC 61800-5-1:2007, 4.3.6 apply.
  2. Measures are taken to ensure that an internal failure of the signal isolation component cannot result in excessive temperature of its insulating material.

Creepage and clearance requirements should be applied according to the specific equipment isolation standards of an application. Care should be taken to maintain the creepage and clearance distance of a board design to ensure that the mounting pads of the isolator on the printed-circuit board do not reduce this distance.