SFFS368 February   2023 LM5148

 

  1.   Trademarks
  2. 1Overview
  3. 2Functional Safety Failure In Time (FIT) Rates
  4. 3Failure Mode Distribution (FMD)
  5. 4Pin Failure Mode Analysis (Pin FMA)

Pin Failure Mode Analysis (Pin FMA)

This section provides a Failure Mode Analysis (FMA) for the pins of the LM5148. The failure modes covered in this document include the typical pin-by-pin failure scenarios:

  • Pin short-circuited to Ground (see Table 4-2)
  • Pin open-circuited (see Table 4-3)
  • Pin short-circuited to an adjacent pin (see Table 4-4)
  • Pin short-circuited to supply (see Table 4-5)

Table 4-2 through Table 4-5 also indicate how these pin conditions can affect the device as per the failure effects classification in Table 4-1.

Table 4-1 TI Classification of Failure Effects
ClassFailure Effects
APotential device damage that affects functionality
BNo device damage, but loss of functionality
CNo device damage, but performance degradation
DNo device damage, no impact to functionality or performance

#GUID-59B67224-3CC4-4810-AE39-411866CAB6F7 shows the LM5148 pin diagram. For a detailed description of the device pins please refer to the Pin Configuration and Functions section in the LM5148 data sheet.

Figure 4-1 Pin Diagram

Following are the assumptions of use and the device configuration assumed for the pin FMA in this section:

  • Application Circuit as per the LM5148 data sheet is used
    • PG is pulled up to VOUT
Table 4-2 Pin FMA for Device Pins Short-Circuited to Ground
Pin NamePin No.Description of Potential Failure Effect(s)Failure Effect Class
NC1NC can be connected to Ground for improved heat spreading.D
NC2NC can be connected to Ground for improved heat spreading.D
CNFG3VOUT is unaffected.C
RT4VOUT will attempt to regulate at maximum fSW, causing maximum power disippation.B
EXTCOMP5VOUT = 0 VB
FB6Internal FB mode, VOUT = expected VOUTD
External FB mode, VOUT = VINA
AGND7AGND is GND. VOUT = expected VOUTD
VDDA8VOUT = 0 V, no switching, loaded VCC outputB
VCC9VOUT = 0 V, no switching, loaded VCC outputB
PGND10PGND is GND. VOUT = expected VOUTD
LO11VOUT = 0 V, the VCC regulator loaded to current limit.B
VIN12VOUT = 0 VB
HO13VOUT = 0 V, the VCC regulator loaded to current limit.B
SW14VOUT = 0 V. High-side FET is shorted from VIN to GND.A
CBOOT15VOUT = 0 V, the VCC regulator loaded to current limit.B
VCCX16VOUT = expected VOUT. Internal VCC regulator provides bias voltage.C
PG17If in single phase, PG has no effect on operation. VOUT = expected VOUTC
If in interleaved primary mode, the secondary will detect no clock input and will shut down. Secondary phase is disabled and primary phase can current limit.B
PFM/SYNC18VOUT = expected VOUT. No synchronization will be available and LM25148/LM25148-Q1 will be in FPWM mode.C
EN19VOUT = 0 V, the LM5148 enters shutdown.C
ISNS+20VOUT = 0 V, HO damagedA
VOUT21VOUT = 0 V. Current limit reached, hiccup mode occurs.B
NC22NC can be connected to Ground for improved heat spreading.D
NC23NC can be connected to Ground for improved heat spreading.D
NC24NC can be connected to Ground for improved heat spreading.D
Table 4-3 Pin FMA for Device Pins Open-Circuited
Pin NamePin No.Description of Potential Failure Effect(s)Failure Effect Class
NC1NC can be open-circuited.D
NC2NC can be open-circuited.D
CNFG3VOUT will continue operating normally. CNFG is used during start-up.C
RT4RT will regulate to 500 mV, but the internal oscillator will not function.B
EXTCOMP5VOUT will oscillate. If VOUT oscillates to VIN, damage can occur if VIN > 36 V.A
FB6Internal FB mode, VOUT = expected VOUTD
External FB mode, VOUT = VINA
AGND7VOUT is indeterminate.B
VDDA8Poor noise immunityC
VCC9VOUT = 0 VB
PGND10VOUT = 0 VB
LO11VOUT = expected VOUT with reduced efficiency.C
VIN12VOUT = 0 VC
HO13If HO is opened while HO to SW has voltage, the high-side FET will never turn off. VOUT = VINA
SW14VOUT is indeterminate. The CBOOT floating rail has no reference to the actual SW node. VOUT = VINA
CBOOT15VOUT = 0 VB
VCCX16VCCX held to ground by weak pulldown, VOUT = expected VOUTD
PG17If in single phase, PG has no effect on operation. VOUT = expected VOUTC
If in interleaved primary mode, the secondary will detect no clock input and will shut down. Secondary phase is disabled and primary phase can current limit.B
PFM/SYNC18VOUT = expected VOUTD
EN19VOUT = expected VOUTD
ISNS+20The OPEN ISNS+ pin will block current limit and cause VOUT oscillations.A
VOUT21VOUT = 0 VB
NC22NC can be open-circuited.D
NC23NC can be open-circuited.D
NC24NC can be open-circuited.D
Table 4-4 Pin FMA for Device Pins Short-Circuited to Adjacent Pin
Pin NamePin No.Shorted toDescription of Potential Failure Effect(s)Failure Effect Class
NC1NCNo impactD
NC2CNFGNo impactD
CNFG3RTVOUT = expected VOUT with erractic switchingB
RT4EXTCOMPCOMP cannot regulate down due to clamping by internal RT. B
EXTCOMP5FBExternal FB mode: COMP will regulate to 0.8 V and output will be unregulated. VOUT = indeterminateB
Internal FB mode: COMP will rise up to VDDA. VOUT = VINA
FB6AGNDExternal FB mode: VOUT = VINA
Internal FB mode: VOUT = expected VOUTD
AGND7VDDAVDDA will be grounded. VOUT = 0 VB
VDDA8VCCVOUT = expected VOUTD
VCC9PGNDVCC will be grounded. VOUT = 0 VB
PGND10LOVOUT = 0 V. VCC is loaded by the LO driver.B
LO11VINVOUT = 0 V. The driver will be damaged if VIN > 6.5 V.A
VIN12HOVOUT = VINA
HO13SWVOUT = 0 VB
SW14CBOOTVOUT = 0 VB
CBOOT15VCCXVOUT < 5 VA
VCCX16PGPG pulldown can damage, VOUT = expected VOUTA
PG17PFM/SYNCVOUT = expected VOUTC
PFM/SYNC18ENVOUT = expected VOUTA
EN19ISNS+EN is high-voltage rated. VOUT = expected VOUT if VOUT > 1 V. If VOUT < 1 V, the device is disabled.B
ISNS+20VOUTCurrent limit is disabled since the current limit resistor would be shorted. VOUT cannot regulate since current mode feedback is shorted.A
VOUT21NCNo impactD
NC22NCNo impactD
NC23NCNo impactD
NC24NCNo impactD
Table 4-5 Pin FMA for Device Pins Short-Circuited to VIN
Pin NamePin No.Description of Potential Failure Effect(s)Failure Effect Class
NC1No impactD
NC2No impactD
CNFG3VOUT = VINA
RT4VOUT = 0 V, high VIN currentA
EXTCOMP5This will bring VDDA up to VIN. VOUT = VINA
FB6This will bring VDDA up to VIN. VOUT = VINA
AGND7VOUT = VIN, high VIN currentA
VDDA8If VIN < 6.5 V, VOUT = expected VOUTD
If VIN > 6.5 V, exceeds maximum ratings and VDDA is damaged.A
VCC9If VIN < 6.5 V, VOUT = expected VOUTD
If VIN > 6.5 V, exceeds maximum ratings and VCC is damaged.A
PGND10VOUT = VIN, high VIN currentA
LO11For VIN < 6.5 V, VOUT = 0; excess current from VINB
For VIN > 6.5 V, exceeds maximum ratings and the LO pin is damaged.A
VIN12N/AD
HO13For VIN < 6.5 V, VOUT = dropout lower than VIN, no switching, and excess current from VINB
For VIN > 6.5 V, exceeds maximum ratings and the HO pin is damaged, VOUT = VINA
SW14VOUT = VIN, excess current from VIN. LO turns on and shorts against VIN.A
CBOOT15For VIN < 6.5 V, VOUT = expected VOUT, erratic switchingB
For VIN > 6.5 V, exceeds maximum ratings and the CBOOT pin is damaged, HO damaged. VOUT = VINA
VCCX16If VCCX = VOUT, for VIN < 6.5 V, VOUT = VINB
For VIN > 6.5 V, exceeds maximum ratings and the VCCX pin is damaged.A
PG17For VIN < 6.5 V, VOUT = regulated and PG forced highB
For VIN > 6.5 V, exceeds maximum ratings and PG is destroyed.A
PFM/SYNC18If PFM = GND, VOUT=0 V, excess current from VINB
If PFM = VDDA and VIN < 6.5 V, VOUT = expected VOUT. Erratic switchingB
If VIN > 6.5 V, exceeds maximum ratings and the PFM/SYNC pin is damaged, VOUT = expected VOUTA
EN19The LM5148 will be always on. VOUT = expected VOUTC
ISNS+20If VIN < 36 V, VOUT = VINB
If VIN > 36 V, exceeds maximum ratings and the CS pin is damaged.A
VOUT21If VIN < 36 V, VOUT = VINB
If VIN > 36 V, exceeds maximum ratings and the CS pin is damaged.A
NC22No impactD
NC23No impactD
NC24No impactD