SFFS549 April   2024 LM7481-Q1

 

  1.   1
  2.   Trademarks
  3. 1Overview
  4. 2Functional Safety Failure In Time (FIT) Rates
  5. 3Failure Mode Distribution (FMD)
  6. 4Pin Failure Mode Analysis (Pin FMA)

Pin Failure Mode Analysis (Pin FMA)

This section provides a Failure Mode Analysis (FMA) for the pins of the LM7481-Q1. The failure modes covered in this document include the typical pin-by-pin failure scenarios:

Table 4-2 through Table 4-5 also indicate how these pin conditions can affect the device as per the failure effects classification in Table 4-1.

Table 4-1 TI Classification of Failure Effects
ClassFailure Effects
APotential device damage that affects functionality
BNo device damage, but loss of functionality
CNo device damage, but performance degradation
DNo device damage, no impact to functionality or performance

Figure 4-1 shows the LM7481-Q1 pin diagram. For a detailed description of the device pins please refer to the Pin Configuration and Functions section in the LM7481-Q1 data sheet.

GUID-D3C13CA3-EC89-46F5-8E03-8136201E3CDE-low.gifFigure 4-1 Pin Diagram

The pin FMA is provided under the assumption that the device is operating under the specified ranges within the Recommended Operating Conditions section of the data sheet.

Table 4-2 Pin FMA for Device Pins Short-Circuited to Ground
Pin NamePin No.Description of Potential Failure Effect(s)Failure Effect Class

DGATE

1

Device will damage due to internal conduction. External DGATE FET can also damage due to maximum VGS rating violation.

A

A

2

Input supply shorted to ground. Device will not be functional.

B

VSNS

3

Input supply monitoring feature will not be available.

B

SW

4

No device damage is expected if VSNS is floating. Device will get damaged if VSNS connected to A.

A

OV

5

Overvoltage protection functionality will be disabled.

B

EN/UVLO

6

Device will be in shutdown mode.

B

GND

7

No impact on the device functionality.

D

HGATE

8

HGATE gate drive will be off.

B

OUT

9

No device damage is expected. External FET VGS(max) rating can exceed and damage external FET.

D

VS

10

Device will not power up.

B

CAP

11

Device will damage due to internal conduction between VS and CAP.

A

C

12

Linear regulation and reverse current blocking functionality will not be available.

B

Table 4-3 Pin FMA for Device Pins Open-Circuited
Pin Name Pin No. Description of Potential Failure Effect(s) Failure Effect Class

DGATE

1

External FET will be off as DGATE drive is open.

B

A

2

Device will not power up.

B

VSNS

3

Input supply monitoring feature will not be available.

B

SW

4

Input supply monitoring feature will not be available.

B

OV

5

Overvoltage functionality is not controlled, it can turn HGATE ON/OFF.

B

EN/UVLO

6

Device will be in shutdown mode due to internal pull-down on EN/UVLO pin.

B

GND

7

Device will not power up.

B

HGATE

8

External high side FET will be off as HGATE gate drive is open.

B

OUT

9

HGATE FET will not be able to turn off as OUT is floating.

B

VS

10

Device will not power up.

B

CAP

11

DGATE and HGATE would turn on and off as part enter CP UVLO cycle due to insufficient decoupling cap.

B

C

12

DGATE drive will be off.

B

Table 4-4 Pin FMA for Device Pins Short-Circuited to Adjacent Pin
Pin Name Pin No.

Shorted to

Description of Potential Failure Effect(s) Failure Effect Class

DGATE

1

A

DGATE FET is always off as external FET GATE to SOURCE is shorted.

B

A

2

VSNS

No impact on device functionality.

D

VSNS

3

SW

Input supply monitoring feature will always be available.

B

SW

4

OV

HGATE will turn off provided SW pin voltage is higher than overvoltage comparator threshold.

B

OV

5

EN/UVLO

HGATE will be on/off based on EN/UVLO voltage level being lower/higher than overvoltage comparator threshold.

B

EN/UVLO

6

No impact on device operation.

D

GND

7

HGATE

HGATE will be pulled low and external FET will be off.

B

HGATE

8

OUT

External HGATE FET will be off as FET GATE to SOURCE is shorted.

B

OUT

9

VS

HGATE FET gets bypassed. Overvoltage protection and load disconnect functionality will not be available.

B

VS

10

CAP

Device will not power up.

B

CAP

11

C

Charge pump will not come up. DGATE and HGATE drives will be off.

B

C

12

No impact on device operation.

D

Table 4-5 Pin FMA for Device Pins Short-Circuited to Supply
Pin Name Pin No. Description of Potential Failure Effect(s) Failure Effect Class

DGATE

1

DGATE FET is always off as external FET GATE to SOURCE is shorted.

B

A

2

No impact on device operation.

D

VSNS

3

No impact on device operation.

D

SW

4

Input supply monitoring feature will always be available.

B

OV

5

HGATE will be off due to overvoltage comparator input higher than overvoltage threshold.

B

EN/UVLO

6

Device will be always on. Undervoltage functionality will not be available.

B

GND

7

Input supply shorted to ground. Device will not power up.

B

HGATE

8

HGATE gate drive will be off and device quiescent current can increase

B

OUT

9

Input is shorted to output. Device functionality will not be available.

B

VS

10

DGATE FET is shorted. Reverse polarity and reverse current blocking feature is not available.

B

CAP

11

Charge pump will not power up. DGATE and HGATE drive will remain off.

B

C

12

Linear regulation and reverse current blocking functionality will not be available.

B