SFFS644 September 2023 LM25185 , LM5185
4 Pin Failure Mode Analysis (Pin FMA)
This section provides a Failure Mode Analysis (FMA) for the pins of the LM5185, LM25185. The failure modes covered in this document include the typical pin-by-pin failure scenarios:
- Pin short-circuited to Ground (see Table 4-2)
- Pin open-circuited (see Table 4-3 )
- Pin short-circuited to an adjacent pin (see Table 4-4)
- Pin short-circuited to supply (see Table 4-5)
Table 4-2 through Table 4-5 also indicate how these pin conditions can affect the device as per the failure effects classification in Table 4-1.
Table 4-1 TI Classification of Failure
Effects
| Class | Failure Effects |
|---|---|
| A | Potential device damage that affects functionality |
| B | No device damage, but loss of functionality |
| C | No device damage, but performance degradation |
| D | No device damage, no impact to functionality or performance |
Figure 4-1 shows the LM5185, LM25185 pin diagram. For a detailed description of the device pins please refer to the Pin Configuration and Functions section in the LM5185, LM25185 data sheets.
Figure 4-1 Pin DiagramFollowing are the assumptions of use and the device configuration assumed for the pin FMA in this section:
- Device used within the Recommended Operating Conditions and the Absolute Maximum Ratings found in the LM5185 and LM25185 data sheet.
- Application circuit as shown in the Application and Implementation section found in the LM5185 and LM25185 data sheet.
Table 4-2 Pin FMA for Device Pins
Short-Circuited to Ground
| Pin Name | Pin No. | Description of Potential Failure Effect(s) | Failure Effect Class |
|---|---|---|---|
| EN | 1 | VOUT = 0 V. Shutdown operation. | B |
| NC | 2 | Normal operation. | D |
| TC | 3 | Temperature compensation disabled; VOUT will be slightly higher than the target due to RTC||RSET. | C |
| RSET | 4 | 120 μs switching, delivering a power of ½ × L × I_pk^2 × fsw to the output. | B |
| AGND | 5 | Normal operation. | D |
| SS | 6 | If short during start-up, delivering a power of ½ × L × I_pk_min^2 × fsw_min (minimum load) to the output. If short during steady-state, normal operation. | B |
| COMP | 7 | Delivering a power of ½ × L × I_pk_min^2 × fsw_min (minimum load) to the output. | B |
| PGND | 8 | Normal operation. | D |
| CS | 9 | Forced maximum ton of 32 us. Can potentially damage the FET and VOUT = 0 V. | A |
| VCC | 10 | VOUT = 0 V. | B |
| GATE | 11 | VOUT = 0 V. Potential damage to VCC and GATE. | A |
| NC | 12 | Normal operation. | D |
| FB | 13 | VOUT = 0 V. Damage the internal VIN to FB diode. | A |
| VIN | 14 | VOUT = 0 V | B |
Table 4-3 Pin FMA for Device Pins
Open-Circuited
| Pin Name | Pin No. | Description of Potential Failure Effect(s) | Failure Effect Class |
|---|---|---|---|
| EN | 1 | Shutdown or normal operation since EN is high impedance | B |
| NC | 2 | Normal operation. | D |
| TC | 3 | VOUT regulating. Temperature compensation disabled. | C |
| RSET | 4 | Delivering a power of ½ × L × I_pk_min^2 × fsw_min (minimum load) to the output. | B |
| AGND | 5 | Floating ground. Vout = 0 V. | B |
| SS | 6 | VOUT regulating. Internal SS. | C |
| COMP | 7 | Loss of loop compensation and the output voltage can oscillate. | B |
| PGND | 8 | Floating ground. Vout = 0 V. External FET can be damaged. | B |
| CS | 9 | VOUT = 0 V. CS is pulled up internally. Device enters hiccup. | B |
| VCC | 10 | High ripple on VCC pin that can trigger VCC UVLO. | B |
| GATE | 11 | VOUT = 0 V. | B |
| NC | 12 | Normal operation. | D |
| FB | 13 | 120 μs switching, delivering a power of ½ × L × I_pk^2 × fsw to the output. | B |
| VIN | 14 | VOUT = 0 V. | B |
Table 4-4 Pin FMA for Device Pins
Short-Circuited to Adjacent Pin
| Pin Name | Pin No. | Description of Potential Failure Effect(s) | Failure Effect Class |
|---|---|---|---|
| EN | 1 | Normal operation. | D |
| NC | 2 | Normal operation. | D |
| TC | 3 | 120 μs switching, delivering a power to the output (the power can be ½ × L × I_pk^2 × fsw, ½ × L × I_pk_min^2 × fsw, or between); TC disabled. | B |
| RSET | 4 | 120 μs switching, delivering a power of ½ × L× I_pk^2 × fsw to the output. | B |
| AGND | 5 | If short during start-up, delivering a power of ½ × L × I_pk_min^2 × fsw_min (minimum load) to the output. If short during steady-state, pin operates normally. | B |
| SS | 6 | VOUT is a little higher than regulation target. Compensation network is changed and output voltage can oscillate. | B |
| COMP | 7 | Corner pin not considered. | NA |
| PGND | 8 | Forced maximum ton of 32 us. Can damage the FET and VOUT = 0 V. | A |
| CS | 9 | VOUT = 0 V. Damage CS pin. | A |
| VCC | 10 | VOUT = 0 V. Damage the gate driver. | A |
| GATE | 11 | Normal operation. | D |
| NC | 12 | Normal operation. | D |
| FB | 13 | VOUT = 0 V. | B |
| VIN | 14 | Corner pin not considered. | NA |
Table 4-5 Pin FMA for Device Pins
Short-Circuited to supply
VIN
| Pin Name | Pin No. | Description of Potential Failure Effect(s) | Failure Effect Class |
|---|---|---|---|
| EN | 1 | VOUT regulating. Always in active mode. | C |
| NC | 2 | Normal operation. | D |
| TC | 3 | Potentially damage TC pin if VIN > 5 V. | A |
| RSET | 4 | Damage RSET pin. | A |
| AGND | 5 | VOUT = 0 V. | B |
| SS | 6 | Potentially damage SS pin if VIN > 5 V. | A |
| COMP | 7 | Potentially damage COMP pin if VIN > 5 V. | A |
| PGND | 8 | VOUT = 0 V. | B |
| CS | 9 | Damage CS pin. | A |
| VCC | 10 | Potentially damage VCC pin if VIN > 15 V. Otherwise Vout regulating with gate drive voltage = VIN. | A |
| GATE | 11 | Potentially damage GATE and VCC pin. | A |
| NC | 12 | Normal operation. | D |
| FB | 13 | VOUT = 0 V. | B |
| VIN | 14 | Normal operation. | D |