SLAA380B December   2007  – September 2018 MSP430F2616 , MSP430F2617 , MSP430F2618 , MSP430F2619

 

  1.   Migrating From MSP430F16x MCUs to MSP430F261x MCUs
    1.     Trademarks
    2. 1 Comparison of MSP430F1xx and MSP430F2xx Families
    3. 2 Hardware Considerations for MSP430F16x to MSP430F261x Migration
      1. 2.1 Device Package and Pinout
      2. 2.2 Current Consumption
      3. 2.3 Operating Frequency and Supply Voltage
      4. 2.4 Device Errata
    4. 3 MSP430F16x to MSP430F261x Migration – Firmware Considerations
      1. 3.1 CPU and Memory Considerations
        1. 3.1.1 Extended Memory Architecture
        2. 3.1.2 Subroutine Parameter Passing and Stack Frame
        3. 3.1.3 MSP430X Instruction Cycle Count Optimizations
        4. 3.1.4 Device Memory Map
        5. 3.1.5 Information Flash Memory
      2. 3.2 Serial Communication – USART Versus USCI
        1. 3.2.1 UART Mode
        2. 3.2.2 SPI Mode
        3. 3.2.3 I2C Mode
      3. 3.3 Clock System
        1. 3.3.1 LFXT1 and XT2 Oscillators
        2. 3.3.2 Digitally Controlled Oscillator (DCO)
      4. 3.4 Bootloader
      5. 3.5 Interrupt Vectors
      6. 3.6 Beware of Reserved Bits!
      7. 3.7 Timers
      8. 3.8 Analog Comparator
    5. 4 References
  2.   Revision History

3.2.2 SPI Mode

The operation of the MSP430F261x USCI in SPI mode and the MSP430F16x USART is almost identical. The major differences are:

  • The MSP430F16x USART supports two channels of simultaneous SPI communication (USART0 and USART1), and the MSP430F261x USCI supports four channels (USCI_A0, USCI_B0, USCI_A1, and USCI_B1).
  • On the MSP430F16x, each of the four SPI communication endpoints has a dedicated interrupt vector. On the MSP430F261x, each USCI module has a two shared interrupt vectors, combining transmit and receive events for each module. On both devices, four interrupt vectors are available in total.
  • The MSP430F261x USCI defaults to an LSB-first SPI bit order. The bit order can be configured with the UCMSB bit in the UCAxCTL0/UCBxCTL0 control registers. This is different compared to the UART module, where the bit order is MSB first and cannot be configured.
  • The maximum MSP430F261x USCI bit clock frequency in SPI master mode is BRCLK, and on the MSP430F16x USART module, it is BRCLK/2.