SLAAE45 September   2021 TMUXHS4412

 

  1.   Trademarks
  2. 1Introduction
  3. 2Practical PCB Design Rules
    1. 2.1 PCIe® Specific Standard
    2. 2.2 PCIe® High-Speed Signal Layout Guidelines
    3. 2.3 Vias, Stub, and ESD/EMI Layout Guidelines
    4. 2.4 Power and Grounding Layout Guidelines
  4. 3Layout Examples
  5. 4Summary
  6. 5References

2.2 PCIe® High-Speed Signal Layout Guidelines

  1. For PCIe® high-speed signals, design trace impedance so as to minimize the reflections in traces. Control the trace impedance to be as close as possible to the recommended values in Table 2-1.
  2. Keep the total trace length for signal pairs to a minimum.
  3. Match the etch lengths of the relevant differential pair traces. Make sure intra-pair skew is within 5 mils for the PCIe® standard. There is no need to match inter-pair skew.
    GUID-D3A253A6-C218-4870-818E-C45B482AF1D7-low.pngFigure 2-1 Differential Pair Intra-Pair Skew and Inter-Pair Skew
  4. To minimize crosstalk in high-speed interface implementations, the spacing between the signal pairs must be a minimum of 5 times the width of the trace.
  5. When possible, route high-speed differential pair signals on the top or bottom layer of the PCB with an adjacent GND layer. TI does not recommend stripline routing of the high-speed differential signals.
  6. Void right-angle bends in a trace and try to route them at least with two 45° corners. To minimize any impedance change, the best routing is a round bend (see Figure 2-2)
GUID-4C205A67-206C-490D-A1BB-54C55D5C9735-low.gifFigure 2-2 Poor and Good Right Angle Bends