SLAZ100AA October 2012 – May 2021 CC430F6127
RF1A Module
Functional
The PLL lock detector output is not 100% reliable
The PLL lock detector output is not 100% reliable and might toggle even if the PLL is in lock. The PLL is in lock if the lock detector output has a positive transition or is constantly logic high. The PLL is not in lock if the lock detector output is constantly logic low. It is not recommended to check for PLL lock by reading PKTSTATUS[0] with GDOx_CFG=0x0A or PKTSTATUS[2] register with GDOx_CFG=0x0A (x = 0 or 2).
PLL lock can be checked reliably by these methods:
- Program register IOCFGx.GDOx_CFG=0x0A and use the lock detector output available on the GDOx pin as an interrupt for the MCU. A positive transition on the GDOx pin means that the PLL is in lock. It is important to disable for interrupt when waking the chip from SLEEP state as the wake-up might cause the GDOx pin to toggle when it is programmed to output the lock detector.
or
- Read register FSCAL1. The PLL is in lock if the register content is different from 0x3F.
With both of the above workarounds the CC1101 PLL calibration should be carried out with the correct settings for TEST0.VCO_SEL_CAL_EN and FSCAL2.VCO_CORE_H_EN. These settings are depending on the operating frequency, and is calculated automatically by SmartRF Studio.
Note that the TEST0 register content is not retained in SLEEP state, and thus it is necessary to write to this register as described
above when returning from the SLEEP state.