SLAZ308AD October   2012  – May 2021 MSP430F5522

 

  1. 1Functional Advisories
  2. 2Preprogrammed Software Advisories
  3. 3Debug Only Advisories
  4. 4Fixed by Compiler Advisories
  5. 5Nomenclature, Package Symbolization, and Revision Identification
    1. 5.1 Device Nomenclature
    2. 5.2 Package Markings
      1.      ZQE80
      2.      RGC64
    3. 5.3 Memory-Mapped Hardware Revision (TLV Structure)
  6. 6Advisory Descriptions
    1. 6.1  ADC25
    2. 6.2  ADC27
    3. 6.3  ADC29
    4. 6.4  ADC42
    5. 6.5  ADC69
    6. 6.6  BSL6
    7. 6.7  BSL7
    8. 6.8  COMP10
    9. 6.9  CPU21
    10. 6.10 CPU22
    11. 6.11 CPU23
    12. 6.12 CPU26
    13. 6.13 CPU27
    14. 6.14 CPU28
    15. 6.15 CPU29
    16. 6.16 CPU30
    17. 6.17 CPU31
    18. 6.18 CPU32
    19. 6.19 CPU33
    20. 6.20 CPU34
    21. 6.21 CPU35
    22. 6.22 CPU37
    23. 6.23 CPU39
    24. 6.24 CPU40
    25. 6.25 CPU47
    26. 6.26 DMA4
    27. 6.27 DMA7
    28. 6.28 DMA8
    29. 6.29 DMA10
    30. 6.30 EEM9
    31. 6.31 EEM11
    32. 6.32 EEM13
    33. 6.33 EEM14
    34. 6.34 EEM15
    35. 6.35 EEM16
    36. 6.36 EEM17
    37. 6.37 EEM19
    38. 6.38 EEM21
    39. 6.39 EEM23
    40. 6.40 FLASH33
    41. 6.41 FLASH34
    42. 6.42 FLASH35
    43. 6.43 FLASH37
    44. 6.44 JTAG20
    45. 6.45 JTAG26
    46. 6.46 JTAG27
    47. 6.47 MPY1
    48. 6.48 PMAP1
    49. 6.49 PMM9
    50. 6.50 PMM10
    51. 6.51 PMM11
    52. 6.52 PMM12
    53. 6.53 PMM14
    54. 6.54 PMM15
    55. 6.55 PMM17
    56. 6.56 PMM18
    57. 6.57 PMM20
    58. 6.58 PORT15
    59. 6.59 PORT16
    60. 6.60 PORT19
    61. 6.61 PORT24
    62. 6.62 RTC3
    63. 6.63 RTC6
    64. 6.64 SYS10
    65. 6.65 SYS12
    66. 6.66 SYS14
    67. 6.67 SYS16
    68. 6.68 SYS18
    69. 6.69 TAB23
    70. 6.70 USB4
    71. 6.71 USB6
    72. 6.72 USB8
    73. 6.73 USB9
    74. 6.74 USB10
    75. 6.75 USB11
    76. 6.76 USB12
    77. 6.77 USB13
    78. 6.78 USCI26
    79. 6.79 USCI30
    80. 6.80 USCI31
    81. 6.81 USCI34
    82. 6.82 USCI35
    83. 6.83 USCI39
    84. 6.84 USCI40
    85. 6.85 WDG4
  7. 7Revision History

PMM9

PMM Module

Category

Functional

Function

False SVSxIFG events

Description

The comparators of the SVS require a certain amount of time to stabilize and output a correct result once re-enabled; this time is different for the Full Performance versus the Normal mode. The time to stabilize the SVS comparators is intended to be accounted for by a built-in event-masking delay of 2 us when Full Performance mode is enabled.
However, the comparators of the SVS in Full Performance mode take longer than 2 us to stabilize so the possibility exists that a false positive will be triggered on the SVSH or SVSL. This results in the SVSxIFG flags being set and depending on the configuration of SVSxPE bit a POR can also be triggered.
Additionally when the SVSxIFGs are set, all GPIOs are tri-stated i.e. floating until the SVSx comparators are settled.

The SVS IFG's are falsely set under the following conditions:

1. Wakeup from LPM2/3/4 when SVSxMD = 0 (default setting) && SVSxFP=1. The SVSx comparators are disabled automatically in LPM2/3/4 and are then re-enabled on return to active mode.

2. SVSx is turned on in full performance mode (SVSxFP=1).

3. A PUC/POR occurs after SVSx is disabled. After a PUC or POR the SVSx are enabled automatically but the settling delay does not get triggered. Based on SVSxPE bit this may lead to POR events until the SVS comparator is fully settled.

Workaround

For each of the above listed conditions the following workarounds apply:

1. If the Full Performance mode is to be enabled for either the high- or low-side SVS comparators, the respective SVSxMD bits must be set (SVSxMD = 1) such that the SVS comparators are not temporarily shut off in LPM2/3/4. Note that this is equivalent to a 2 uA (typical) adder to the low power mode current, per the device-specific datasheet, for each SVSx that remains enabled.

2. The SVSx must be turned on in normal mode (SVSxFP=0). It can be reconfigured to use full performance mode once the SVSx/SVMx delay has expired.

3. Ensure that SVSH and SVSL are always enabled.