SLLA611 september 2023 TDP1204
This section explores the effects on the HDMI 2.1 waveforms by experimenting with the different receiver EQ, VoD and termination register settings. While performing these register changes, the different effects on the waveforms are provided for both linear and limited redriver modes.
The effects that the TDP1204 controls have on the eye diagram differ between linear and limited mode. The selection between the redriver modes is done by setting the most significant bit (MSB) of the GBL_CTRL1 Register (Offset = 0xDh). If the GLOBAL_LINR_EN is set to 0 then the redriver functions in limited mode. If the GLOBAL_LINR_EN is set to 1 then the redriver functions in the linear mode. The two least significant bits of the GBL_CTRL1 Register are used to control the termination settings of the device. The TDP1204 TX termination can be set to one of four settings: No termination (TERM = 0x0), 300-ohms (TERM = 0x1), Automatic based HDMI mode (TERM = 0x2) or 100-ohms (TERM = 0x3).
The EQ and VoD settings can be modified for each lane independently. Therefore, there are four registers that can be modified for each of the four HDMI 2.1 FRL data lanes.
To choose between the receiver EQ settings, set the least four significant bits of the following registers: CLK_CONFIG2 Register (Offset = 0x13h), D0_CONFIG2 Register (Offset = 0x15h), D1_CONFIG2 Register (Offset = 0x17h) and D2_CONFIG2 Register (Offset = 0x19h).
To choose between the VoD settings for HDMI 2.1 FRL, set the least three significant bits of the following registers: CLK_CONFIG1 Register (Offset = 0x12h), D0_CONFIG1 Register (Offset = 0x14h), D1_CONFIG1 Register (Offset = 0x16h) and D2_CONFIG1 Register (Offset = 0x18h). The CLK_CONFIG registers map to the D3 data lane of HDMI 2.1 FRL.
Please refer to TDP1204 12-Gbps, DC/AC-Coupled to HDMI™ 2.1 Level Shifter Hybrid Redriver, data sheet for more information on these registers.