SLUAAG4 February   2022 TPS62933

 

  1.   Trademarks
  2. 1Introduction
  3. 2Loop Response of Peak Current Mode Converter
  4. 3Output Capacitance Upper Limit for Internally-Compensated PCM Buck Converter
  5. 4Output Capacitance Lower Limit for Internally-Compensated PCM Buck Converter
  6. 5Design Example and Experimental Validation for TPS62933
  7. 6Summary
  8. 7References
  9.   A Validation and Calculating the Output Capacitance Upper Limit

5 Design Example and Experimental Validation for TPS62933

Figure 5-1 illustrates the conclusion of the application design method.

Figure 5-1 TPS62933 Application Design Flow Chart

Take the typical application as an example: Vin = 24 V, Vout = 5 V, Iout = 3 A, fsw = 1200 kHz.

Based on the inductor selection method introduced in the data sheet, choose an inductance of 3.3 μH for the application.

Here the upper limit of output capacitance is verified. The CO upper limit of 119.6 μF is obtained with Equation 12 for –20 dB/dec crossing and also CO upper limit of 131 μF for 45 degree phase margin restriction.

Note here the calculated CO is the effective value.

The example is validated on the EVM. The C3216X5R1V226M160AC (22 μF) and CGA5L1X7R1H106K160AC (10 μF) are selected here as CO. When biased at 5 V, the effective of C3216X5R1V226M160AC is about 13.2 μF and the effective of CGA5L1X7R1H106K160AC is about 9.4 μF.

The upper output capacitance limit is verified with choosing CO = 8 × 22 μF. The effective capacitance is about 105.6 μF and slightly lower than the upper limit of 119.6 μF. Figure 5-2 shows the phase margin is 45.827 degrees.

Figure 5-2 Bode Plot for Output Capacitance Lower Limit Validation

The test results in Figure 5-2 show the effectiveness of the proposed method. See more validation results in Section A.