SLUAAG5 March   2022 TPS62933

 

  1.   Trademarks
  2. 1Introduction
  3. 2Cff in High-Output Voltage Internally Compensated PCM Buck Converter
  4. 3Effects of Cff on the Loop
  5. 4Method for Selecting Cff
  6. 5Experimental Verification for TPS62933
  7. 6Summary
  8. 7References
  9.   A Validation Results for the Proposed Method

2 Cff in High-Output Voltage Internally Compensated PCM Buck Converter

Loop Response Considerations in Peak Current Mode Buck Converter Design introduces the loop response model of PCM mode buck converters, as shown in Figure 2-1. The initial loop gain slope of the PCM converter is 0, it changes from 0 to –20 dB/dec at the initial pole frequency fP1_EA. At pole fP_OUT, the loop gain slope changes to –40 dB/dec. With the compensation of zero fZ_EA, the gain slope becomes –20 dB/dec, and the gain curve crosses 0 dB with a –20-dB/dec slope. That slope can normally bring sufficient phase margin for the converter.

The TPS62933 has internal compensation, the fP1_EA, fZ_EA, and fP2_EA are the frequencies of poles and zero generated by the internal compensation and fixed as Equation 1:

Equation 1.
Figure 2-1 Bode Plot of PCM Buck Converter Open Loop Response

The DC gain Adc is related with output current. The Adc of TPS62933 can be expressed as:

Equation 2.

fP_OUT is the frequency of the pole formed with the output capacitance and loading, which can be expressed as:

Equation 3.

The expressions of Adc and fP_OUT include the output current Iout and the load resistance RO, respectively.

For the application with a fixed load resistance RO, when output voltage increases, output current increases and the DC gain Adc decreases. As Figure 2-2 illustrates, this causes the bandwidth decrease. If the zero fZ_EA becomes out of bandwidth, the –40 dB/decade gain slope occurs at gain crossover frequency and could cause insufficient phase margin.

Figure 2-2 Loop Gain of TPS62933 With Fixed Load Resistance RO (a) Low VO With –20 dB/dec Crossing (b) High Vo With –40 dB/dec Crossing

For converters with fixed output current Iout, the equivalent output resistance RO increases with increasing output voltage, which makes the frequency fP_OUT in Equation 3 decrease. As Figure 2-3 shows, that results in bandwidth decrease and could also cause the compensated zero fZ_EA to become out of bandwidth. The –40 dB/decade gain slope also occurs at gain crossover frequency and could cause insufficient phase margin.

Figure 2-3 Loop Gain of TPS62933 With Constant Output Current Iout (a) Low Vo With –20 dB/dec Crossing (b) High Vo With –40 dB/dec Crossing

Above all, increasing output voltage tends to cause the internal peak-current-mode converter to be unstable, which makes it hard to design an application with high output voltage.

Since the pole frequency fP_OUT is inversely proportional to the output capacitance Co, reducing Co can help to increase the frequency fP_OUT, making the zero fZ_EA inside bandwidth again and bringing enough phase margin. Just as the derived output capacitance range with Equation 4 in Part I, the maximum output capacitance is reduced by increasing the output voltage VO for stability. But reducing output capacitance has many side effects, such as poor transient performance, larger ripple, and larger noise.

Equation 4.

This analysis proves that in high-voltage applications, there is a contradiction between performance and stability in an internally-compensated PCM buck converter. Adding a feedforward capacitor Cff can help solve the issue at this condition.