6 Stability Design Method

To make sure of the system stability margin, the recommendation is that the loop gain needs to cross 0dB with -20dB/dec slope. By adjusting the frequencies of those poles and zeros shown in Figure 5-3, there can be many different approaches to achieve the target. This application note only proposes one simplified stability design method as reference.

1. f_Z-EA < f_cross, f_P-ci > f_cross and f_P2-EA > f_cross

   In the stability design of normal PCM buck converter without 2^nd stage filter, it’s recommended to make f_Z-EA smaller than bandwidth f_cross and keep the f_P-ci & f_P2-EA larger than bandwidth, which can make loop gain cross 0dB with -20dB/dec slope ^[5-6]. Those design limitations are inherited in this design method.

2. Keep all the zeros and poles introduced by second stage filter out of bandwidth, including:
   • f_Zff > f_cross

     If the zero Z_ff is inside bandwidth, it can further increase converter bandwidth f_cross and improve dynamic response. But that would make it more difficult to estimate the bandwidth and cause more uncertainties. To simplify the stability design, f_Zff>f_cross is given as a restriction. Typically, the bandwidth of PCM converter is set as f_cross≤f_SW/10.

     Since the expression of f_Zff in Equation 23 is very complicated, an example of how to use Microsoft® Excel® or MATLAB® to calculate f_Zff is introduced in Appendix A.

   • f_P-2nd > 2 x f_cross

     Recommend to keep f_P-2nd > 2 x f_cross to avoid effects of the conjugate poles on phase margin. Combined with Equation 22, the range of the 2^nd stage filter capacitor C₂ can be derived as:

     Equation 24. ${\text{L}}_{\text{2}}\text{<}\frac{\left(\frac{\text{1}}{{\text{C}}_{\text{2}}}+\frac{\text{1}}{{\text{C}}_{\text{O}}}\right)}{\text{16}{\text{π}}^{\text{2}}{{\text{f}}_{\text{cross}}}^{\text{2}}}$

     The bandwidth f_cross with 2^nd stage filter can be received with Equation 25.

     Equation 25. ${\text{f}}_{\text{cross}}\text{≈}\frac{{\text{V}}_{\text{ref}}{\text{G}}_{\text{m}}{\text{R}}_{\text{comp}}}{{\text{2πV}}_{\text{out}}{\text{R}}_{\text{i}}\left({\text{C}}_{\text{O}}\text{+}{\text{C}}_{\text{2}}\right)}$

     For specific device TPS62933F, the bandwidth f_cross is:

     Equation 26. ${\text{f}}_{\text{cross}}\text{≈}\frac{\text{6.35}}{{\text{V}}_{\text{out}}\left({\text{C}}_{\text{O}}\text{+}{\text{C}}_{\text{2}}\right)}$
3. Avoid second gain crossing through damping effects of L₂ DC resistance

   As mentioned in section 5, the conjugate zeros Z_2nd are located in the right half plane with negative damping, if considering L₂ as an designed for inductor with no DCR.

   The same effect for lack of damping also exists on the conjugate poles P_2nd. Those effects can cause resonance peak and loop gain may crosses 0dB twice, as shown in the case DCR_L2=0 of Figure 6-1.

Figure 6-1 PCM Converter Loop Response with Second Stage Filter When Changing DCR_L2

The second gain crossing has a chance to cause system instability ^[7]. Like the example in Figure 6-1, increasing DCR_L2 can effectively reduce the resonance peak amplitude and avoid second gain crossing. Increasing conjugate poles frequency f_P-2nd is another approach to avoid second gain crossing, like shown in Figure 6-2.

Figure 6-2 PCM Converter Loop Response with Second Stage Filter When Changing f_P-2nd

As second gain crossing does not normally happen with DCR_L2 of real inductor or ferrite bead (several mΩ or larger), further mathematical analysis is not included in this application note. But the above two methods can be tried, if you already follow the design flow in next section, but there is still instability issue.