SLUS659G FEBRUARY   2006  – November 2014 TPS40200

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 Handling Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 MOSFET Gate Drive
      2. 7.3.2 Undervoltage Lockout Protection
      3. 7.3.3 Selecting the Operating Frequency
      4. 7.3.4 Synchronizing the Oscillator
      5. 7.3.5 Current Limit Resistor Selection
      6. 7.3.6 Calculating the Soft-Start Time
      7. 7.3.7 Voltage Setting and Modulator Gain
    4. 7.4 Device Functional Modes
      1. 7.4.1 Operation Near Minimum Input Voltage
      2. 7.4.2 Operation With SS Pin
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Buck Regulator, 8 V to 12 V Input, 3.3 V to 5.0 V at 2.5-A Output
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
          1. 8.2.1.2.1 FET Selection Criteria
          2. 8.2.1.2.2 Rectifier Selection Criteria
          3. 8.2.1.2.3 Inductor Selection Criteria
          4. 8.2.1.2.4 Output Capacitance
          5. 8.2.1.2.5 Switching Frequency
          6. 8.2.1.2.6 Calculating the Overcurrent Threshold Level
          7. 8.2.1.2.7 Soft-Start Capacitor
          8. 8.2.1.2.8 Frequency Compensation
            1. 8.2.1.2.8.1 Step 1
            2. 8.2.1.2.8.2 Step 2
            3. 8.2.1.2.8.3 Step 3
            4. 8.2.1.2.8.4 Step 4
            5. 8.2.1.2.8.5 Step 5
          9. 8.2.1.2.9 Printed Circuit Board Plots
        3. 8.2.1.3 Application Curves
      2. 8.2.2 18 V - 50 V Input, 16 V at 1-A Output
        1. 8.2.2.1 Design Requirements
        2. 8.2.2.2 Detailed Design Procedures
        3. 8.2.2.3 Application Curves
      3. 8.2.3 Wide Input Voltage Led Constant Current Driver
        1. 8.2.3.1 Design Requirements
        2. 8.2.3.2 Detailed Design Procedures
        3. 8.2.3.3 Application Curve
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 Related Products
      2. 11.1.2 Third-Party Products Disclaimer
    2. 11.2 Documentation Support
      1. 11.2.1 Related Documentation
    3. 11.3 Trademarks
    4. 11.4 Electrostatic Discharge Caution
    5. 11.5 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

5 Pin Configuration and Functions

VSON (DRB) PACKAGE
8 PINS
(BOTTOM VIEW)
pinout_qfn_lus659.gif
SOIC (D) PACKAGE
8 PINS
(TOP VIEW)
pinout_soic_lus659.gif

Pin Functions

PIN I/O DESCRIPTION
NAME NO.
COMP 3 O Error amplifier output. Connect control loop compensation network from COMP to FB.
FB 4 I Error amplifier inverting input. Connect feedback resistor network center tap to this pin.
GND 5 Device ground.
GDRV 6 O Driver output for external P-channel MOSFET
ISNS 7 I Current-sense comparator input. Connect a current sense resistor between ISNS and VDD in order to set desired overcurrent threshold.
RC 1 I Switching frequency setting RC network. Connect a capacitor from the RC pin to the GND pin and connect a resistor from the VDD pin to the RC pin. The device may be synchronized to an external clock by connecting an open drain output to this pin and pulling it to GND. For mor info on pulse width for synchronization, please refer to the Synchronizing the Oscillator section.
SS 2 I Soft-start programming pin. Connect capacitor from SS to GND to program soft start time. Pulling this pin below 150 mV causes the output switching to stop, placing the device in a shutdown state. The pin also functions as a restart timer for overcurrent events.
VDD 8 I System input voltage. Connect local bypass capacitor from VDD to GND.