SLUUCJ0 November   2023 BQ76907

 

  1.   1
  2.   Read This First
    1.     About This Manual
    2.     Battery Notational Conventions
    3.     Trademarks
    4.     Glossary
  3. 1 Introduction
  4. 2 Device Description
    1. 2.1 Overview
    2. 2.2 Functional Block Diagram
  5. 3 Device Configuration
    1. 3.1 Direct Commands and Subcommands
    2. 3.2 Configuration Using OTP or Registers
    3. 3.3 Data Formats
      1. 3.3.1 Unsigned Integer
      2. 3.3.2 Integer
      3. 3.3.3 Hex
  6. 4 Device Security
  7. 5 Measurement Subsystem
    1. 5.1 Voltage Measurement
      1. 5.1.1 Voltage Measurement Schedule
      2. 5.1.2 Unused VC Cell Input Pins
      3. 5.1.3 General Purpose ADCIN Functionality
    2. 5.2 Coulomb Counter and Digital Filters
    3. 5.3 Internal Temperature Measurement
    4. 5.4 Thermistor Temperature Measurement
    5. 5.5 Measurement Calibration
  8. 6 Protection Subsystem
    1. 6.1  Protections Overview
    2. 6.2  Protection FET Drivers
    3. 6.3  Cell Overvoltage Protection
    4. 6.4  Cell Undervoltage Protection
    5. 6.5  Short Circuit in Discharge Protection
    6. 6.6  Overcurrent in Charge Protection
    7. 6.7  Overcurrent in Discharge 1 and 2 Protections
    8. 6.8  Current Protection Latch
    9. 6.9  CHG Detector
    10. 6.10 Overtemperature in Charge Protection
    11. 6.11 Overtemperature in Discharge Protection
    12. 6.12 Internal Overtemperature Protection
    13. 6.13 Undertemperature in Charge Protection
    14. 6.14 Undertemperature in Discharge Protection
    15. 6.15 Host Watchdog Protection
    16. 6.16 Cell Open Wire Detection
    17. 6.17 Voltage Reference Measurement Diagnostic Protection
    18. 6.18 VSS Measurement Diagnostic Protection
    19. 6.19 REGOUT Diagnostic Protection
    20. 6.20 LFO Oscillator Integrity Diagnostic Protection
    21. 6.21 Internal Factory Trim Diagnostic Protection
  9. 7 Device Status and Controls
    1. 7.1 0x00 Control Status() and 0x12 Battery Status() Commands
    2. 7.2 LDOs
    3. 7.3 ALERT Pin Operation
    4. 7.4 TS Pin Operation
    5. 7.5 Programmable Timer
    6. 7.6 Device Event Timing
  10. 8 Operational Modes
    1. 8.1 Overview of Operational Modes
    2. 8.2 NORMAL Mode
    3. 8.3 SLEEP Mode
    4. 8.4 DEEPSLEEP Mode
    5. 8.5 SHUTDOWN Mode
    6. 8.6 CONFIG_UPDATE Mode
  11. 9 I2C Serial Communications
    1. 9.1 I2C Serial Communications Interface
  12. 10Cell Balancing
    1. 10.1 Cell Balancing
  13. 11Commands and Subcommands
    1. 11.1 Direct Commands
    2. 11.2 Bit field Definitions for Direct Commands
      1. 11.2.1  Safety Alert A Register
      2. 11.2.2  Safety Status A Register
      3. 11.2.3  Safety Alert B Register
      4. 11.2.4  Safety Status B Register
      5. 11.2.5  Battery Status Register
      6. 11.2.6  Alarm Status Register
      7. 11.2.7  Alarm Raw Status Register
      8. 11.2.8  Alarm Enable Register
      9. 11.2.9  FET CONTROL Register
      10. 11.2.10 REGOUT CONTROL Register
      11. 11.2.11 DSG FET Driver PWM Control Register
      12. 11.2.12 CHG FET Driver PWM Control Register
    3. 11.3 Command-only Subcommands
    4. 11.4 Subcommands with Data
    5. 11.5 Bit field Definitions for Subcommands
      1. 11.5.1 DEVICE NUMBER Register
      2. 11.5.2 FW VERSION Register
      3. 11.5.3 HW VERSION Register
      4. 11.5.4 SECURITY KEYS Register
      5. 11.5.5 CB ACTIVE CELLS Register
      6. 11.5.6 PROG TIMER Register
      7. 11.5.7 PROT RECOVERY Register
  14. 12Data Memory
    1. 12.1 Calibration
      1. 12.1.1 Calibration:Voltage
        1. 12.1.1.1 Calibration:Voltage:Cell 1 Gain
        2. 12.1.1.2 Calibration:Voltage:Cell 2 Gain Delta
        3. 12.1.1.3 Calibration:Voltage:Cell 3 Gain Delta
        4. 12.1.1.4 Calibration:Voltage:Cell 4 and 5 Gain Delta
        5. 12.1.1.5 Calibration:Voltage:Cell 6 and 7 Gain Delta
        6. 12.1.1.6 Calibration:Voltage:Stack Gain
      2. 12.1.2 Calibration:Current
        1. 12.1.2.1 Calibration:Current:Curr Gain
        2. 12.1.2.2 Calibration:Current:Curr Offset
        3. 12.1.2.3 Calibration:Current:CC1 Gain
        4. 12.1.2.4 Calibration:Current:CC1 Offset
      3. 12.1.3 Calibration:Temperature
        1. 12.1.3.1 Calibration:Temperature:TS Offset
        2. 12.1.3.2 Calibration:Temperature:Int Temp Gain
        3. 12.1.3.3 Calibration:Temperature:Int Temp Offset
    2. 12.2 Settings
      1. 12.2.1 Settings:Configuration
        1. 12.2.1.1 Settings:Configuration:Power Config
        2. 12.2.1.2 Settings:Configuration:REGOUT Config
        3. 12.2.1.3 Settings:Configuration:I2C Address
        4. 12.2.1.4 Settings:Configuration:I2C Config
        5. 12.2.1.5 Settings:Configuration:DA Config
        6. 12.2.1.6 Settings:Configuration:Vcell Mode
        7. 12.2.1.7 Settings:Configuration:Default Alarm Mask
        8. 12.2.1.8 Settings:Configuration:FET Options
        9. 12.2.1.9 Settings:Configuration:Charge Detector Time
      2. 12.2.2 Settings:Cell Balancing
        1. 12.2.2.1 Settings:Cell Balancing:Balancing Configuration
        2. 12.2.2.2 Settings:Cell Balancing:Min Temp Threshold
        3. 12.2.2.3 Settings:Cell Balancing:Max Temp Threshold
        4. 12.2.2.4 Settings:Cell Balancing:Max Internal Temp
      3. 12.2.3 Settings:Protection
        1. 12.2.3.1 Settings:Protection:Enabled Protections A
        2. 12.2.3.2 Settings:Protection:Enabled Protections B
        3. 12.2.3.3 Settings:Protection:DSG FET Protections A
        4. 12.2.3.4 Settings:Protection:CHG FET Protections A
        5. 12.2.3.5 Settings:Protection:Both FET Protections B
        6. 12.2.3.6 Settings:Protection:Body Diode Threshold
        7. 12.2.3.7 Settings:Protection:Cell Open Wire NORMAL Check Time
        8. 12.2.3.8 Settings:Protection:Cell Open Wire SLEEP Check Time
        9. 12.2.3.9 Settings:Protection:Host Watchdog Timeout
    3. 12.3 Protections
      1. 12.3.1 Protections:Cell Voltage
        1. 12.3.1.1 Protections:Cell Voltage:Cell Undervoltage Protection Threshold
        2. 12.3.1.2 Protections:Cell Voltage:Cell Undervoltage Protection Delay
        3. 12.3.1.3 Protections:Cell Voltage:Cell Undervoltage Protection Recovery Hysteresis
        4. 12.3.1.4 Protections:Cell Voltage:Cell Overvoltage Protection Threshold
        5. 12.3.1.5 Protections:Cell Voltage:Cell Overvoltage Protection Delay
        6. 12.3.1.6 Protections:Cell Voltage:Cell Overvoltage Protection Recovery Hysteresis
      2. 12.3.2 Protections:Current
        1. 12.3.2.1  Protections:Current:Overcurrent in Charge Protection Threshold
        2. 12.3.2.2  Protections:Current:Overcurrent in Charge Protection Delay
        3. 12.3.2.3  Protections:Current:Overcurrent in Discharge 1 Protection Threshold
        4. 12.3.2.4  Protections:Current:Overcurrent in Discharge 1 Protection Delay
        5. 12.3.2.5  Protections:Current:Overcurrent in Discharge 2 Protection Threshold
        6. 12.3.2.6  Protections:Current:Overcurrent in Discharge 2 Protection Delay
        7. 12.3.2.7  Protections:Current:Short Circuit in Discharge Protection Threshold
        8. 12.3.2.8  Protections:Current:Short Circuit in Discharge Protection Delay
        9. 12.3.2.9  Protections:Current:Latch Limit
        10. 12.3.2.10 Protections:Current:Recovery Time
      3. 12.3.3 Protections:Temperature
        1. 12.3.3.1  Protections:Temperature:Overtemperature in Charge Protection Threshold
        2. 12.3.3.2  Protections:Temperature:Overtemperature in Charge Protection Delay
        3. 12.3.3.3  Protections:Temperature:Overtemperature in Charge Protection Recovery
        4. 12.3.3.4  Protections:Temperature:Undertemperature in Charge Protection Threshold
        5. 12.3.3.5  Protections:Temperature:Undertemperature in Charge Protection Delay
        6. 12.3.3.6  Protections:Temperature:Undertemperature in Charge Protection Recovery
        7. 12.3.3.7  Protections:Temperature:Overtemperature in Discharge Protection Threshold
        8. 12.3.3.8  Protections:Temperature:Overtemperature in Discharge Protection Delay
        9. 12.3.3.9  Protections:Temperature:Overtemperature in Discharge Protection Recovery
        10. 12.3.3.10 Protections:Temperature:Undertemperature in Discharge Protection Threshold
        11. 12.3.3.11 Protections:Temperature:Undertemperature in Discharge Protection Delay
        12. 12.3.3.12 Protections:Temperature:Undertemperature in Discharge Protection Recovery
        13. 12.3.3.13 Protections:Temperature:Internal Overtemperature Protection Threshold
        14. 12.3.3.14 Protections:Temperature:Internal Overtemperature Protection Delay
        15. 12.3.3.15 Protections:Temperature:Internal Overtemperature Protection Recovery
    4. 12.4 Power
      1. 12.4.1 Power:Sleep
        1. 12.4.1.1 Power:Sleep:Sleep Current
        2. 12.4.1.2 Power:Sleep:Voltage Time
        3. 12.4.1.3 Power:Sleep:Wake Comparator Current
      2. 12.4.2 Power:Shutdown
        1. 12.4.2.1 Power:Shutdown:Shutdown Cell Voltage
        2. 12.4.2.2 Power:Shutdown:Shutdown Stack Voltage
        3. 12.4.2.3 Power:Shutdown:Shutdown Temperature
        4. 12.4.2.4 Power:Shutdown:Auto Shutdown Time
    5. 12.5 Security
      1. 12.5.1 Security:Settings
        1. 12.5.1.1 Security:Settings:Security Settings
        2. 12.5.1.2 Security:Settings:Full Access Key Step 1
        3. 12.5.1.3 Security:Settings:Full Access Key Step 2
    6. 12.6 Data Memory Summary
  15. 13Revision History

5.1.1 Voltage Measurement Schedule

Overview

The voltage ADC and associated mux operates on a measurement loop to implement all its required measurements. The schedule is different in NORMAL versus SLEEP mode (there are no measurements in DEEPSLEEP or SHUTDOWN modes).

NORMAL Mode Scheduling

The measurement loop in NORMAL mode consists of a fast ADSCAN loop, which consists of up to 8 separate measurement slots. The width of the measurement slots is independently programmable based on the category of measurement - cell voltage measurement vs other measurements. By programming the width of the slot, the effective resolution of the ADC conversion changes with it. The slot width is programmable as 366 μs (fastest but lowest resolution), 732 μs, 1.46 ms, or 2.93 ms (slowest but highest resolution). The schedule of conversions while in NORMAL mode is described in the tables below. If a device is configured to use fewer than the maximum number of supported series cells (such as the device being used in a 3s system), the schedule is shortened accordingly. This results in the number of slots in an ADSCAN in NORMAL mode being (number of cells used) + 1.

Table 5-2 NORMAL Mode Voltage ADC ADSCAN Measurement Loop (setup for a 7s configuration)
Slot NumberSelected Input
0Cell-1 Voltage
1Cell-2 Voltage
2Cell-3 Voltage
3Cell-4 Voltage
4Cell-5 Voltage
5 Cell-6 Voltage
6 Cell-7 Voltage
7Shared Slot
Table 5-3 NORMAL Mode Voltage ADC ADSCAN Measurement Loop (setup for a 2s configuration)
Slot NumberSelected Input
0Cell-1 Voltage
1Cell-2 Voltage
2Shared Slot

The additional measurements that are less speed critical use the Shared Slot, which rotates through a series of five less frequent measurements. The completion of one full rotation through all five of these less frequent measurements (one per ADSCAN loop) is termed a FULLSCAN loop. The items measured in the FULLSCAN using the Shared Slot are shown in the table below. This schedule uses 5 ADSCANs to complete one FULLSCAN to provide updated data for all less frequent measurements. The timing of a FULLSCAN loop depends on the timing of the ADSCAN loop and can range from approximately 5.5 ms to approximately 117 ms (and longer based on the LOOP_SLOW settings described below).

Table 5-4 NORMAL Mode Voltage Schedule - FULLSCAN Shared Slot Usage
Shared Slot UsageDescription
TSMeasurement of TS pin voltage, which can be configured in thermistor mode (with internal pullup enabled and using internal 1.8-V LDO as reference) or general purpose ADCIN mode (with internal pullup disabled and using bandgap reference)
Internal TemperatureMeasurement of delta-VBE
StackTop of stack voltage (VC7 pin) vs VSS, using resistive divider only switched on during measurement.
VREFMeasurement of the internal REG18 LDO voltage
VSSMeasurement of the VSS pin voltage

The measurement of the internal REG18 LDO voltage (which is set based on VREF2) provides an output code given by REG18 × 32768 × 2 / 5 / VREF1, which results in a nominal value of 19228.

The BQ76907 also includes an option to slow the measurement loop if active power dissipation is more important than speed of data availability. The loop can be slowed by up to 8x in NORMAL mode using the Settings:Configuration:Power Config[LOOP_SLOW[1:0]] bits, which cause the voltage ADC to insert idle slots to effectively slow the average conversion speed and thus reduces the device's average power dissipation. See below for how these bits control the schedule. The idle slots are inserted in a contiguous group at the end of each active ADSCAN, not interleaved between each active conversion slot, to ensure that cell voltage measurements are taken as closely together as possible. The LOOP_SLOW setting does not affect the schedule during SLEEP mode.

Table 5-5 LOOP_SLOW Speed Control
LOOP_SLOW[1]LOOP_SLOW[0]Loop Speed
00Loop runs at full speed
01Loop runs at half speed (one idle slot included for each active slot)
10Loop runs at quarter speed (three idle slots included for each active slot)
11Loop runs at eighth speed (seven idle slots included for each active slot)

SLEEP Mode Scheduling

When the device is in SLEEP mode, measurements are only taken in a burst every Power:Sleep:Voltage Time interval. Between these bursts, the ADC remains idle, to save power. When the timer expires, the device takes all measurements in a long burst. These are implemented as shown in the table below. When fewer than 7 cells are being used, the unused cell voltage slots are removed. This results in the SLEEP schedule length in slots = 5 + (number of cells used).

Table 5-6 SLEEP Mode Measurement Schedule (all 7 cells used)
SlotDescription
0Cell-1 Voltage
1Cell-2 Voltage
2Cell-3 Voltage
3Cell-4 Voltage
4Cell-5 Voltage
5 Cell-6 Voltage
6 Cell-7 Voltage
7TS pin measurement
8Internal Temperature measurement
9Stack measurement
10REG18 measurement
11VSS measurement

When a burst measurement is complete, the device sets the ADSCAN and FULLSCAN bits in Alarm Raw Status() momentarily.

When the device exits SLEEP mode (whether through current detection or command or a protection), it immediately runs a SLEEP mode burst measurement to collect updated data, then begins the NORMAL mode schedule. If a burst measurement is already in progress when the exit is triggered, that burst is completed, and then the device begins the NORMAL mode schedule.

Startup Mode Scheduling

When the device first boots from SHUTDOWN or exits DEEPSLEEP or CONFIG_UPDATE modes, a special fast startup schedule is used, which is similar to the SLEEP mode schedule, but with fixed OSR settings, as shown below. This schedule results in approximately 7 ms ADC conversion time, in addition to the time required for the REG18 LDO to power up from SHUTDOWN. The device then transitions to evaluating the protections, so the FETs can be enabled as quickly as possible. This measurement loop and evaluation completion trigger the INITCOMP bit in Alarm Raw Status(). If the host intends to manually enable the FET drivers, it can monitor this signal to determine when the startup data is available for reading.

Table 5-7 Startup Mode Measurement Schedule (7s version)
SlotDescriptionADC OSR
0Cell-1 Voltage96
1Cell-2 Voltage96
2Cell-3 Voltage96
3Cell-4 Voltage96
4Cell-5 Voltage96
5 Cell-6 Voltage 96
6 Cell-7 Voltage 96
7TS pin measurement384
8Internal Temperature measurement384
9Stack measurement96
10REG18 measurement96
11VSS measurement96

If the device has been configured for a fewer number of cells being used (such as configured for use with only 2 cells being used), the startup sequence is shortened by skipping unused cell measurements. If the device is powering from SHUTDOWN mode, it determines the cell configuration based on the settings read in from OTP. If the device is exiting DEEPSLEEP or CONFIG_UPDATE mode, it uses the cell configuration information previously loaded, either from OTP at power up or modified by the host.