SLUUCJ2 July   2021 UCC14240-Q1

 

  1.   Trademarks
  2. 1Introduction
    1. 1.1 Pin Configuration and Functions
  3. 2Description
    1. 2.1 EVM Electrical Performance Specifications
  4. 3Schematic
  5. 4EVM Setup and Operation
    1. 4.1 Reference
    2. 4.2 External Connections for Easy Evaluation
    3. 4.3 Powering the EVM
      1. 4.3.1 Power on for Start-up
      2. 4.3.2 Power off for Shutdown
    4. 4.4 EVM Test Points
    5. 4.5 Oscilloscope Probes: Probing the EVM
  6. 5 Performance Data
    1. 5.1 Efficiency Data
    2. 5.2 Regulation Data
    3. 5.3 Start-up Waveforms
    4. 5.4 Inrush Current
    5. 5.5 AC Ripple Voltage
    6. 5.6 EN and /PG Timing
    7. 5.7 Shutdown
    8. 5.8 Steady State
    9. 5.9 Thermal Performance
  7. 6Assembly and Printed Circuit Board (PCB) Layers
  8. 7Bill of Materials (BOM)
  9. 8Revision History

Pin Configuration and Functions



Figure 1-1 DWN Package, 36-Pin SSOP (Top View)
Table 1-1 Pin Functions
PIN TYPE1 DESCRIPTION
NAME NO.
GNDP 1, 2, 5, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18 G Primary-side ground connection for VIN. Place several vias to copper pours for thermal relief. .
/PG 3 O

Active low powergood open-drain output pin. /PG pulled low when (UVLO ≤ VIN ≤ OVLO); (UVP1 ≤ (VDD - VEE) ≤ OVP1); (UVP2 ≤ (COM - VEE) ≤ OVP2); TJ_Primary ≤ TSHUT_primary; & TJ_secondary ≤ TSHUT_secondary

ENA 4 I Enable pin. Forcing ENA LOW disables the device. Pull HIGH to enable normal device functionality. 5.5-V recommended maximum.
VIN 6, 7 P Primary input voltage. Connect a 2.2-µF ceramic capacitor from VIN to GNDP. Connect a 150-pF highfrequency bypass ceramic capacitor close the pins.
VEE 19, 20, 21, 22, 23, 24, 25,26, 27, 30,31, 36 G

Secondary-side Reference connection for VDD and COM. The VEE pins are used for the high current return paths.

VDD 28, 29 P Secondary-side isolated output voltage from transformer. Connect a 2.2-µF and a parallel 150-pF ceramic capacitor from VDD to VEE. The 150 pF is the high frequency bypass and should be next to the IC.
RLIM 32 P Secondary-side second isolated output voltage resistor to limit the source current from VDD to COM node, and the sink current from COM to VEE. Connect a resistor from RLIM to COM to regulate the (COM – VEE) voltage.
FBVEE 33 I Feedback (COM – VEE) output voltage sense pin used to adjust the output (COM – VEE) voltage. Connect a resistor divider from COM to VEE so that the midpoint is connected to FBVEE, and the equivalent FBVEE voltage when regulating is 2.5 V.
FBVDD 34 I Feedback (VDD – VEE) output voltage sense pin and to adjust the output (VDD – VEE) voltage. Connect a resistor divider from VDD to VEE so that the midpoint is connected to FBVDD, and the equivalent FBVDD voltage when regulating is 2.5 V.
VEEA 35 G Secondary-side analog sense reference connection for the noise sensitive analog feedback inputs, FBVDD and FBVEE. Low-side resistors and filter capacitor. Connect to secondary-side gate drive lowest voltage reference, VEE. Use a single point connection ans place the high frequency ceramic capacitor close to the VEEA pin.
  1. P = power, G = ground, I = input, O = output