SLVAEQ4A March 2020 – July 2020 TPD3S714-Q1
The failure mode distribution estimation for TPD3S714-Q1 in Table 3-1 comes from the combination of common failure modes listed in standards such as IEC 61508 and ISO 26262, the ratio of sub-circuit function size and complexity and from best engineering judgment.
The failure modes listed in this section reflect random failure events and do not include failures due to misuse or overstress.
| Die Failure Modes | Failure Mode Distribution (%) |
|---|---|
| BUS_CON no output | 25% |
| BUS_CON not in specification – voltage or timing | 20% |
| VD+/D+, VD-/D- no output | 25% |
| VD+/D+, VD-/D- not in specification – voltage or timing | 20% |
| FLT false trip or fails to trip | 5% |
| Short circuit any two pins | 5% |