Throughout this report, there are other losses that were not taken in consideration such as reverse recovery loss of body diode, output capacitance loss of MOSFET, dead time loss, gate charge loss, and IC operation loss. All of these contribute to a certain extent to the total losses. However, our focus in this report is on mid-voltage (3 V to 17 V input), 0.5 MHz to 3 MHz switching frequencies, up to 3 A, 0.4 V to 5.5 V output voltage. For that, the majority of the losses are coming from conduction loss in the high-side MOSFET, conduction loss in the low-side MOSFET, switching-loss in the high-side MOSFET, conduction loss in the inductor, and conduction loss in the input and output capacitor. Looking at the equations provided in the previous sections, the takeaway from this is as follows:

• The R_DS(ON) of the high and low side FETs of the converter needs to be as small as possible. There is a trade off for that, as the R_DS(ON) becomes smaller, silicon area tends to be bigger and more expensive. There is a balance between cost and R_DS(ON). TPS62903 provides a balance between cost and R_DS(ON) value. It is 62 mΩ for high-side FET and 22 mΩ for low-side FET and provides a very good efficiency at both high and low load.
• The switching frequency is another important factor and needs to be taken into consideration. Higher switching frequencies lead to higher switching losses. However, if the switching frequency is reduced too much, the inductor current ripple increases with it and thus will require a bigger inductance. A bigger inductor comes with cost, size, and higher DC resistance. Higher DC resistance affects the inductor power loss as described in the previous sections. A good balance between the switching frequency, inductor current ripple, inductance, size, and cost all has to be weighted equally to find the most favorable conditions. In our analysis, a good range of the inductance for the TPS62903 is found at anything between 0.68 µH to 2.2 µH depending on Fsw, V_IN, and V_OUT.
  1. The 0.68 µH is recommended for:
     • Low V_OUT < 1 V applications for 1 MHz
     • Low V_IN < 10 V applications for 2.5 MHz
  2. The 1 µH is recommended for:
     • Low V_OUT < 1.5 V applications for 1 MHz
     • All voltages at 2.5 MHz
  3. The 2.2 µH recommended for both 2.5 MHz and 1 MHz. Lower frequency provides better efficiency in most cases.

• Using the TPS62903 MODE/S-CONF pin, the user has the option to select Forced Pulse Width Modulation (FPWM) Operation or Auto Pulse Frequency Modulation/ Pulse Width Modulation (Auto PFM/PWM) Operation. In the FPWM mode, the switching frequency variation is well controlled and limited. This is good for filtering the switching noise as the switching frequency variation is limited. However, the efficiency at light load will be inferior than in Auto mode. This is because, in Auto PFM/PWM, the switching frequency decreases linearly with the load current maintaining high efficiency at light load. See Figure 2-1 to compare the efficiency between the two modes.
  
  
  Figure 2-1 Efficiency Comparison at Auto PFM/PWM vs FPWM
• Lower the DCR of the inductor. For 0.68 µH to 2.2 µH inductance range, there is a wide variety of inductors to choose from, and the trade off is the cost and the size. Lowering the DCR typically comes in bigger packages and costs more. It is recommended to use 10 mΩ to 30 mΩ DCR inductors for best efficiency and they come with reasonable package size and cost.
• Lower the output and input capacitor ESR. It is recommended to choose a low-ESR multilayer ceramic capacitor (MLCC) and should be placed as close as possible to the device pins.
• Lower quiescent current of the device helps on the light load efficiency. This is not very helpful in heavy load as other losses are more dominant. In power save mode, the TPS92903 has only 4 µA quiescent current.