SLVS451G September   2003  – December 2014

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Typical Schematic
  5. 5 Revision History
  6. 6 Device Comparison Table
  7. 7 Pin Configuration and Functions
  8. 8 Specifications
    1. 8.1 Absolute Maximum Ratings
    2. 8.2 ESD Ratings
    3. 8.3 Recommended Operating Conditions
    4. 8.4 Thermal Information
    5. 8.5 Electrical Characteristics
    6. 8.6 Typical Characteristics
  9. 9 Parameter Measurement Information
  10. 10Detailed Description
    1. 10.1 Overview
    2. 10.2 Functional Block Diagram
    3. 10.3 Feature Description
      1. 10.3.1 Controller Circuit
      2. 10.3.2 Synchronous Rectifier
      3. 10.3.3 Down Regulation
      4. 10.3.4 Device Enable
      5. 10.3.5 Undervoltage Lockout
      6. 10.3.6 Softstart and Short Circuit Protection
      7. 10.3.7 Low Battery Detector Circuit—LBI/LBO
      8. 10.3.8 Low-EMI Switch
    4. 10.4 Device Functional Modes
      1. 10.4.1 Undervoltage Lockout
      2. 10.4.2 Power Save Mode
    5. 10.5 Programming
      1. 10.5.1 Programming the Output Voltage
      2. 10.5.2 Programming the LBI/LBO Threshold Voltage
  11. 11Application and Implementation
    1. 11.1 Application Information
    2. 11.2 Typical Application
      1. 11.2.1 Design Requirements
      2. 11.2.2 Detailed Design Procedure
        1. 11.2.2.1 Inductor Selection
        2. 11.2.2.2 Input Capacitor Selection
        3. 11.2.2.3 Output Capacitor Selection
      3. 11.2.3 Application Curves
    3. 11.3 System Examples
  12. 12Power Supply Recommendations
  13. 13Layout
    1. 13.1 Layout Guidelines
    2. 13.2 Layout Example
    3. 13.3 Thermal Considerations
  14. 14Device and Documentation Support
    1. 14.1 Device Support
      1. 14.1.1 Third-Party Products Disclaimer
    2. 14.2 Related Links
    3. 14.3 Trademarks
    4. 14.4 Electrostatic Discharge Caution
    5. 14.5 Glossary
  15. 15Mechanical, Packaging, and Orderable Information

8 Specifications

8.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)(1)
MIN MAX UNIT
Input voltage on SW, VOUT, LBO, VBAT, PS, EN, FB, LBI –0.3 7 V
TJ Operating virtual junction temperature –40 150 °C
Tstg Storage temperature –65 150 °C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

8.2 ESD Ratings

VALUE UNIT
V(ESD) Electrostatic discharge Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) ±2000 V
Charged-device model (CDM), per JEDEC specification JESD22-C101(2) ±750
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. Manufacturing with less than 500-V HBM is possible with the necessary precautions.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. Manufacturing with less than 250-V CDM is possible with the necessary precautions.

8.3 Recommended Operating Conditions

MIN NOM MAX UNIT
Supply voltage at VBAT, VI (TPS61020, TPS61024, TPS61025, TPS61028) 0.9 6.5 V
Supply voltage at VBAT, VI (TPS61026, TPS61029) 0.9 5.5 V
Operating virtual junction temperature range, TJ –40 125 °C

8.4 Thermal Information

THERMAL METRIC(1) TPS6102x UNIT
SON
10 PINS
RθJA Junction-to-ambient thermal resistance 47.2 °C/W
RθJC(top) Junction-to-case (top) thermal resistance 67.5
RθJB Junction-to-board thermal resistance 21.6
ψJT Junction-to-top characterization parameter 1.7
ψJB Junction-to-board characterization parameter 21.8
RθJC(bot) Junction-to-case (bottom) thermal resistance 3.6
(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.

8.5 Electrical Characteristics

Over recommended junction temperature range and over recommended input voltage range. Typical values are at TJ = 25°C (unless otherwise noted).
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
DC-DC STAGE
VI Minimum input voltage for start-up RL = 120 Ω 0.9 1.2 V
Input voltage range, after start-up (TPS61020, TPS61024, TPS61025, TPS61027, TPS61028) 0.9 6.5 V
Input voltage range, after start-up (TPS61026, TPS61029) 0.9 5.5 V
VO TPS61020, TPS61028 and TPS61029 output voltage range 1.8 5.5 V
VFB TPS61020, TPS61028 and TPS61029 feedback voltage 490 500 510 mV
f Oscillator frequency 480 600 720 kHz
ISW Switch current limit (TPS61020, TPS61024, TPS61025, TPS61027) VOUT= 3.3 V 1200 1500 1800 mA
ISW Switch current limit (TPS61028) VOUT= 3.3 V 800 mA
ISW Switch current limit (TPS61026, TPS61029) VOUT= 3.3 V 1500 1800 2100 mA
Start-up current limit 0.4 x ISW mA
SWN switch on resistance VOUT= 3.3 V 260 mΩ
SWP switch on resistance VOUT= 3.3 V 290 mΩ
Total accuracy (including line and load regulation) ±3%
Line regulation 0.6%
Load regulation 0.6%
Quiescent current VBAT IO = 0 mA, VEN = VBAT = 1.2 V,
VOUT = 3.3 V, TA = 25°C		 1 3 µA
VOUT 25 45 µA
Shutdown current VEN = 0 V, VBAT = 1.2 V,
TA = 25°C		 0.1 1 µA
CONTROL STAGE
VUVLO Under voltage lockout threshold VLBI voltage decreasing 0.8 V
VIL LBI voltage threshold VLBI voltage decreasing 490 500 510 mV
LBI input hysteresis 10 mV
LBI input current EN = VBAT or GND 0.01 0.1 µA
VOL LBO output low voltage VO = 3.3 V, IOI = 100 µA 0.04 0.4 V
Vlkg LBO output leakage current VLBO = 7 V 0.01 0.1 µA
VIL EN, PS input low voltage 0.2 × VBAT V
VIH EN, PS input high voltage 0.8 × VBAT V
EN, PS input current Clamped on GND or VBAT 0.01 0.1 µA
Overtemperature protection 140 °C
Overtemperature hysteresis 20 °C

8.6 Typical Characteristics

Table 1. Table of Graphs

FIGURE
Maximum output current vs Input voltage (TPS61020) Figure 1
Efficiency vs Output current (TPS61020) Figure 2
vs Output current (TPS61025) Figure 3
vs Output current (TPS61027) Figure 4
vs Input voltage (TPS61025) Figure 5
vs Input voltage (TPS61027) Figure 6
Output voltage vs Output current (TPS61025) Figure 7
vs Output current (TPS61027) Figure 8
No load supply current into VBAT vs Input voltage Figure 9
No load supply current into VOUT vs Input voltage Figure 10
TPS61020 TPS61024 TPS61025 TPS61026 TPS61027 TPS61028 TPS61029 maxio_v_vi_lvs451.gif
Figure 1. TPS61020 Maximum Output Current vs Input Voltage
TPS61020 TPS61024 TPS61025 TPS61026 TPS61027 TPS61028 TPS61029 eff25_v_io_lvs451.gif
Figure 3. TPS61025 Efficiency vs Output Current
TPS61020 TPS61024 TPS61025 TPS61026 TPS61027 TPS61028 TPS61029 eff25_v_vi_lvs451.gif
Figure 5. TPS61025 Efficiency vs Input Voltage
TPS61020 TPS61024 TPS61025 TPS61026 TPS61027 TPS61028 TPS61029 vo25_v_io_lvs451.gif
Figure 7. TPS61025 Output Voltage vs Output Current
TPS61020 TPS61024 TPS61025 TPS61026 TPS61027 TPS61028 TPS61029 nl_vbat_vi_lvs451.gif
Figure 9. No Load Supply Current Into VBAT vs Input Voltage
TPS61020 TPS61024 TPS61025 TPS61026 TPS61027 TPS61028 TPS61029 eff20_v_io_lvs451.gif
Figure 2. TPS61020 Efficiency vs Output Current
TPS61020 TPS61024 TPS61025 TPS61026 TPS61027 TPS61028 TPS61029 eff27_v_io_lvs451.gif
Figure 4. TPS61027 Efficiency vs Output Current
TPS61020 TPS61024 TPS61025 TPS61026 TPS61027 TPS61028 TPS61029 eff27_v_vi_lvs451.gif
Figure 6. TPS61027 Efficiency vs Input Voltage
TPS61020 TPS61024 TPS61025 TPS61026 TPS61027 TPS61028 TPS61029 vo27_v_io_lvs451.gif
Figure 8. TPS61027 Output Voltage vs Output Current
TPS61020 TPS61024 TPS61025 TPS61026 TPS61027 TPS61028 TPS61029 nl_vout_vi_lvs451.gif
Figure 10. No Load Supply Current Into VOUT vs Input Voltage