SLVU793A October   2012  – June 2021 TPS56921

 

  1.   Trademarks
  2. 1Introduction
    1. 1.1 Background
    2. 1.2 Performance Specification Summary
    3. 1.3 Modifications
      1. 1.3.1 Output Voltage Setpoint
      2. 1.3.2 Slow-Start Time
      3. 1.3.3 Adjustable UVLO
      4. 1.3.4 Input Voltage Rails
  3. 2Test Setup and Results
    1. 2.1 Input/Output Connections
    2. 2.2 Efficiency
    3. 2.3 Output Voltage Load Regulation
    4. 2.4 Output Voltage Line Regulation
    5. 2.5 Load Transients
    6. 2.6 Loop Characteristics
    7. 2.7 Output Voltage Ripple
    8. 2.8 Input Voltage Ripple
    9. 2.9 Powering Up
  4. 3Board Layout
    1. 3.1 Layout
  5. 4Schematic and Bill of Materials
    1. 4.1 Schematic
    2. 4.2 Bill of Materials
  6. 5Revision History

3.1 Layout

The board layout for the TPS56921EVM-188 is shown in Figure 3-1 through Figure 3-5. The top-side layer of the EVM is laid out in a manner typical of a user application. The top, bottom, and internal layers are 2-oz. copper.

The top layer contains the main power traces for PVIN, VIN, VOUT, and VPHASE. Also on the top layer are connections for the remaining pins of the TPS56921 and a large area filled with ground. The internal layer-1 is dedicated to a power ground plane. the internal layer-2 contains an analog ground fill area. This analog ground is used as a return for the I2C interface as well as for sensitive analog circuits for RT, SS, EN, COMP and VSENSE. The analog ground is connected to the main power ground at one place to inhibit circulating currents. This connection is made at the via near TP7. Internal layer-2 also contains additional fill areas for PVIN and VOUT, as well as connections to the I2C interface connector at J3. The bottom layer contains a power ground plane only. The top-side ground traces are connected to the bottom and internal ground planes with multiple vias placed around the board including nine vias directly under the TPS56921 and 12 vias directly adjacent to the TPS56921device to provide a thermal path from the top-side ground area to the internal layer-1 and bottom-side ground planes.

The input decoupling capacitors (C1,C2, C3 and C4) and bootstrap capacitor (C8) are all located as close to the IC as possible. Additionally, the voltage setpoint resistor divider components are kept close to the IC. The voltage divider network ties to the output voltage at the point of regulation, the copper VOUT trace at the J4 output connector. For the TPS56921, an additional input bulk capacitor may be required, depending on the EVM connection to the input supply.

GUID-ABB4D2D4-BE8E-4F53-A9A2-DCE34F7613B4-low.gifFigure 3-1 TPS56921EVM-188 Top-Side Assembly
GUID-241272DE-844E-49BC-BB18-289CFA51CA31-low.gifFigure 3-3 TPS56921EVM-188 Internal Layer-1 Layout
GUID-0C04A589-E342-4604-874C-25EBB0A7DD0F-low.gifFigure 3-5 TPS56921EVM-188 Bottom-Side Layout
GUID-8DEB3834-69C9-49AF-BC96-FD8B222B8169-low.gifFigure 3-2 TPS56921EVM-188 Top-Side Layout
GUID-DF22F5E5-A4A2-4BA0-A1C5-ED74B294A33E-low.gifFigure 3-4 TPS56921EVM-188 Internal Layer-2 Layout