SLVUCR8A September 2023 – March 2024 TPS25751

3 TPS25751 Registers

Table 3-1 lists the memory-mapped registers for the TPS25751 registers. All register offset addresses not listed in Table 3-1 should be considered as reserved locations and the register contents should not be modified.

Table 3-1 TPS25751 Registers

Offset	Acronym	Register Name	Section
3h	Mode	Mode	Section 3.1
6h	Customer Use	Customer Use	Section 3.2
8h	Command Register for I2C1	Command Register for I2C1	Section 3.3
9h	Data Register for CMD1	Data Register for CMD1	Section 3.4
14h	Interrupt Event for I2C1	Interrupt Event for I2C1	Section 3.5
16h	Interrupt Mask for I2C1	Interrupt Mask for I2C1	Section 3.6
18h	Interrupt Clear for I2C1	Interrupt Clear for I2C1	Section 3.7
1Ah	Status	Status	Section 3.8
26h	Power Path Status	Power Path Status	Section 3.9
28h	Port Configuration	Port Configuration	Section 3.10
29h	Port Control	Port Control	Section 3.11
2Dh	Boot Flags	Boot Flags	Section 3.12
30h	Received Source Capabilities	Received Source Capabilities	Section 3.13
31h	Received Sink Capabilities	Received Sink Capabilities	Section 3.14
32h	Transmit Source Capabilities	Transmit Source Capabilities	Section 3.15
33h	Transmit Sink Capabilities	Transmit Sink Capabilities	Section 3.16
34h	Active PDO Contract	Active PDO Contract	Section 3.17
35h	Active RDO Contract	Active RDO Contract	Section 3.18
37h	Autonegotiate Sink	Autonegotiate Sink	Section 3.19
3Fh	Power Status	Power Status	Section 3.20
40h	PD Status	PD Status	Section 3.21
5Ch	IO Config	IO Config	Section 3.22
69h	Type C State	Type C State	Section 3.23
6Ah	ADC Results	ADC Results	Section 3.24
70h	Sleep Control Register	Sleep Control Register	Section 3.25
72h	GPIO Status	GPIO Status	Section 3.26
98h	Liquid Detection Config	Liquid Detection Config	Section 3.27

Complex bit access types are encoded to fit into small table cells. Table 3-2 shows the codes that are used for access types in this section.

Table 3-2 TPS25751 Access Type Codes

Access Type	Code	Description
Read Type
R	R	Read
Write Type
W	W	Write
Reset or Default Value
-n		Value after reset or the default value

3.1 Mode Register (Offset = 3h) [Reset = 00000000h]

Mode is shown in Table 3-3.

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Indicates the operational state of the port. The PD controller has limited functionality in some modes.

Table 3-3 Mode Register Field Descriptions

Bit	Field	Type	Reset	Description
31-0	Mode	R	0h	The mode described in 4 ASCII characters. 'APP ' indicates that the PD controller is fully functioning in the application firmware where all registers are available. 'BOOT' indicates that the PD controller is booting in dead battery. 'PTCH' indicates that the PD controller is in patch mode. Any other values indicates that the PD controller is functioning in limited capacity. In 'BOOT' and 'PTCH' only the follow register addresses are accessible, Mode, Command, Data, Int Event, Int Mask, Int Clear, and Boot Flags.

3.2 Customer Use Register (Offset = 6h) [Reset = 0000000000000000h]

Customer Use is shown in Table 3-4.

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These 8 bytes are allocated for customer use as needed. The PD controller does not use this register. This register may be changed during application customization.

Table 3-4 Customer Use Register Field Descriptions

Bit	Field	Type	Reset	Description
63-0	Customer Use	R	0h	These 8 bytes are allocated for customer use as needed. The PD controller does not use this register. This register may be changed during application customization.

3.3 Command Register for I2C1 (Offset = 8h) [Reset = 00000000h]

Command Register for I2C1 is shown in Table 3-5.

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Command register for the primary command interface. Cleared to 0x0000_0000 by the PD Controller during initialization and after successful processing of every command. If an unrecognized command is written to this register, it is replaced by a 4CC value of "!CMD".

Table 3-5 Command Register for I2C1 Field Descriptions

Bit	Field	Type	Reset	Description
31-0	Command	R/W	0h	Command register for the primary command interface. Cleared to 0x0000_0000 by the PD Controller during initialization and after successful processing of every command. If an unrecognized command is written to this register, it is replaced by a 4CC value of "!CMD".

3.4 Data Register for CMD1 (Offset = 9h) [Reset = 00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000h]

Data Register for CMD1 is shown in Table 3-6.

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Data register for the primary command interface (CMD1).

Table 3-6 Data Register for CMD1 Field Descriptions

Bit	Field	Type	Reset	Description
511-0	Data	R/W	0h	Data register for the primary command interface (CMD1).

3.5 Interrupt Event for I2C1 Register (Offset = 14h) [Reset = 0000000000000002000008h]

Interrupt Event for I2C1 is shown in Table 3-7.

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Interrupt event bit field for IRQ. If any bit in this register is 1, then the IRQ pin is pulled low. Bytes 1 to 10 of this register are port-specific, but Byte 11( Bits 80-87) is common to all ports in the PD controller.

Table 3-7 Interrupt Event for I2C1 Register Field Descriptions

Bit	Field	Type	Reset	Description
87-83	RESERVED	R	0h	Reserved
82	I2C Controller NACked	R	0h	A transaction on the I2C Controller was NACKed.
81	Ready for Patch	R	0h	Device ready for a patch bundle from the host.
80	Patch Loaded	R	0h	Patch was loaded to the device.
79	RESERVED	R	0h	Reserved
78	RESERVED	R	0h	Reserved
77	RESERVED	R	0h	Reserved
76	RESERVED	R	0h	Reserved
75-74	RESERVED	R	0h	Reserved
73	RESERVED	R	0h	Reserved
72	RESERVED	R	0h	Reserved
71	RESERVED	R	0h	Reserved
70	RESERVED	R	0h	Reserved
69-67	RESERVED	R	0h	Reserved
66	MBRD Buffer Ready	R	0h	Receive memory buffer full and ready to be read using the 'MBRd' command.
65	TX Memory Buffer Empty	R	0h	Transmit memory buffer empty.
64	RESERVED	R	0h	Reserved
63	RESERVED	R	0h	Reserved
62	RESERVED	R	0h	Reserved
61	RESERVED	R	0h	Reserved
61	RESERVED	R	0h	Reserved
60	Liquid Detection	R	0h	Asserted when Liquid Detection is detected or removed. Read 0x98 to determine the state of Liquid Detection.
60	RESERVED	R	0h	Reserved
59	RESERVED	R	0h	Reserved
62-59	RESERVED	R	0h	Reserved
58	RESERVED	R	0h	Reserved
57	Ext DCDC Source Safe State	R	0h	Used for EC controlled battery charger or DC/DC applications to indicate when the PD controller is no longer going to act as a source. This interrupt will be set when acting as a source and receiving/sending an Accept message to a Power Role Swap.
56	Ext DCDC Sink Safe State	R	0h	Used for EC controlled battery charger or DC/DC applications to indicate when the PD controller is no longer going to act as a sin. This interrupt will be set when acting as a sink and receiving/sending an Accept message to a Power Role Swap. This interrupt will also be set when acting as a sink and receiving an Explicit PD Contract Accept from the connected source.
55	RESERVED	R	0h	Reserved
54	RESERVED	R	0h	Reserved
53	RESERVED	R	0h	Reserved
52	RESERVED	R	0h	Reserved
51	RESERVED	R	0h	Reserved
50	RESERVED	R	0h	Reserved
49	RESERVED	R	0h	Reserved
48	RESERVED	R	0h	Reserved
47	RESERVED	R	0h	Reserved
46	Unable to Source Error	R	0h	The Source was unable to increase the voltage to the negotiated voltage of the contract.
45	RESERVED	R	0h	Reserved
44	RESERVED	R	0h	Reserved
43	Plug Early Notification	R	0h	A connection has been detected but not debounced.
42	Sink Transition Completed	R	0h	This event only occurs when in source mode (PD_STATUS.PresentPDRole = 1b). It occurs tSrcTransition (ms) after sending an Accept message to a Request message, just before sending the PS_RDY message.
41-40	RESERVED	R	0h	Reserved
39	Message Data Error	R	0h	An erroneous message was received.
38	Protocol Error	R	0h	An unexpected message was received from the partner device.
37	RESERVED	R	0h	Reserved
36	Missing Get Capabilities Message Error	R	0h	The partner device did not respond to the Get_Sink_Cap or Get_Source_Cap message that was sent.
35	Power Event Occurred Error	R	0h	An OVP, or ILIM event occurred on VBUS. Or a TSD event occurred.
34	Can Provide Voltage or Current Later Error	R	0h	The USB PD Source can provide acceptable voltage and current, but not at the present time. A "wait" message was sent or received.
33	Cannot Provide Voltage or Current Error	R	0h	The USB PD Source cannot provide an acceptable voltage and/or current. A Reject message was sent to the Sink or a Capability Mismatch was received from the Sink.
32	Device Incompatible Error	R	0h	When set to 1, a USB PD device with an incompatible specification version was connected. Or the partner device is not USB PD capable.
31	RESERVED	R	0h	Reserved
30	CMD1 Complete	R	0h	Set whenever a non-zero value in CMD1 register is set to zero or !CMD.
29-28	RESERVED	R	0h	Reserved
27	PD Status Updated	R	0h	Set whenever contents of PD_STATUS register (0x40) change.
26	Status Updated	R	0h	Set whenever contents of STATUS register (0x1A) change.
25	RESERVED	R	0h	Reserved
24	Power Status Updated	R	0h	Set whenever contents of POWER_STATUS register (0x3F) change.
23	Power Path Switch Changed	R	0h	Set whenever contents of POWER_PATH_STATUS register (0x26) changes.
22	RESERVED	R	0h	Reserved
21	USB Host No Longer Present	R	0h	Set when STATUS.UsbHostPresent transitions to anything other than 11b.
20	USB Host Present	R	0h	Set when STATUS.UsbHostPresent transitions to 11b.
19	RESERVED	R	0h	Reserved
18	Data Swap Requested	R	0h	A DR swap was requested by the Port Partner.
17	Power Swap Requested	R	0h	A PR swap was requested by the Port Partner.
16	RESERVED	R	0h	Reserved
15	Sink Cap Message Received	R	0h
14	Source Capabilities Message Received	R	0h	This is asserted when a Source Capabilities message is received from the Port Partner.
13	New Contract as Provider	R	0h	An RDO from the far-end device has been accepted and the PD Controller is a Source. This is asserted after the PS_RDY message has been sent. See ACTIVE_CONTRACT_PDO register (0x34) and ACTIVE_CONTRACT_RDO register (0x35) for details.
12	New Contract as Consumer	R	0h	Far-end source has accepted an RDO sent by the PD Controller as a Sink. See ACTIVE_CONTRACT_PDO register (0x34) and ACTIVE_CONTRACT_RDO register (0x35) for details.
11	RESERVED	R	0h	Reserved
10	RESERVED	R	0h	Reserved
9	Overcurrent	R	0h	Set whenever an Overcurrent field (VBUS or VCONN) in the POWER_PATH_STATUS register (0x26) changes.
8	RESERVED	R	0h	Reserved
7	RESERVED	R	0h	Reserved
6	RESERVED	R	0h	Reserved
5	Data Swap Complete	R	0h	A Data Role swap has completed. See STATUS register (0x1A) and PD_STATUS register (0x40) for port state.
4	Power Swap Complete	R	0h	A Power role swap has completed. See STATUS register (0x1A) and PD_STATUS register (0x40) for port state.
3	Plug Insert or Removal	R	1h	USB Plug Status has Changed. See Status register for more plug details.
2	RESERVED	R	0h	Reserved
1	PD Hardreset	R	0h	A PD Hard Reset has been performed. See PD_STATUS.HardResetDetails for more information.
0	RESERVED	R	0h	Reserved

3.6 Interrupt Mask for I2C1 Register (Offset = 16h) [Reset = 0000000000000000030000h]

Interrupt Mask for I2C1 is shown in Table 3-8.

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Interrupt mask bit field for INT_EVENT1. A bit in INT_EVENT1 cannot be set if it is cleared in this register. Bytes 1 to 10 of this register are port-specific, but Byte 11( Bits 80-87) is common to all ports in the PD controller.

Table 3-8 Interrupt Mask for I2C1 Register Field Descriptions

Bit	Field	Type	Reset	Description
87-83	RESERVED	R/W	0h	Reserved
82	I2C Controller NACKed	R/W	0h
81	Ready for Patch	R/W	0h
80	Patch Loaded	R/W	0h
79	RESERVED	R/W	0h
78	RESERVED	R/W	0h
77	RESERVED	R/W	0h
76	RESERVED	R/W	0h
75	RESERVED	R/W	0h
74	RESERVED	R/W	0h
73	RESERVED	R/W	0h	Reserved
72	RESERVED	R/W	0h
71	RESERVED	R/W	0h
70	RESERVED	R/W	0h
69	RESERVED	R/W	0h
68	RESERVED	R/W	0h
67	RESERVED	R/W	0h
66	MBRD Buffer Ready	R/W	0h
65	TX Memory Buffer Empty	R/W	0h
64	RESERVED	R/W	0h
63	RESERVED	R/W	0h
62	RESERVED	R/W	0h
61	RESERVED	R/W	0h	Reserved
60	Liquid Detection	R/W	0h	Liquid Detection
59	RESERVED	R/W	0h
58	RESERVED	R/W	0h
57	Ext DCDC Source Safe State	R/W	0h
56	Ext DCDC Sink Safe State	R/W	0h
55	RESERVED	R/W	0h
54	RESERVED	R/W	0h
53	RESERVED	R/W	0h
52	RESERVED	R/W	0h
51	RESERVED	R/W	0h
50	RESERVED	R/W	0h
49	RESERVED	R/W	0h
48	RESERVED	R/W	0h
47	RESERVED	R/W	0h	Reserved
46	Unable to Source Error	R/W	0h
45	RESERVED	R/W	0h	Reserved
44	RESERVED	R/W	0h
43	Plug Early Notification	R/W	0h
42	Sink Transition Completed	R/W	0h
41	RESERVED	R/W	0h
40	RESERVED	R/W	0h	Reserved
39	Message Data Error	R/W	0h
38	Protocol Error	R/W	0h
37	RESERVED	R/W	0h	Reserved
36	Missing Get Capabilities Message Error	R/W	0h
35	Power Event Occurred Error	R/W	0h
34	Can Provide Voltage or Current Later Error	R/W	0h
33	Cannot Provide Voltage or Current Error	R/W	0h
32	Device Incompatible Error	R/W	0h
31	RESERVED	R/W	0h
30	CMD1 Complete	R/W	0h
29-28	RESERVED	R/W	0h	Reserved
27	PD Status Updated	R/W	0h
26	Status Updated	R/W	0h
25	RESERVED	R/W	0h
24	Power Status Updated	R/W	0h
23	Power Path Switch Changed	R/W	0h
22	RESERVED	R/W	0h	Reserved
21	USB Host No Longer Present	R/W	0h
20	USB Host Present	R/W	0h
19	RESERVED	R/W	0h	Reserved
18	Data Swap Requested	R/W	0h
17	Power Swap Requested	R/W	1h
16-15	RESERVED	R/W	0h	Reserved
14	Source Cap Message Received	R/W	0h
13	New Contract as Provider	R/W	0h
12	New Contract as Consumer	R/W	0h
11	RESERVED	R/W	0h
10	RESERVED	R/W	0h
9	Overcurrent	R/W	0h
8-7	RESERVED	R/W	0h	Reserved
6	RESERVED	R/W	0h
5	Data Swap Complete	R/W	0h
4	Power Swap Complete	R/W	0h
3	Plug Insert or Removal	R/W	0h
2	RESERVED	R/W	0h	Reserved
1	PD Hardreset	R/W	0h
0	RESERVED	R/W	0h	Reserved

3.7 Interrupt Clear for I2C1 Register (Offset = 18h) [Reset = 0000000000000000000000h]

Interrupt Clear for I2C1 is shown in Table 3-9.

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Interrupt clear bit field for INT_EVENT1. Writing 1 to a specific bit will clear that specific event in INT_EVENT1. Bits set in this register are cleared from INT_EVENT1. Bytes 1 to 10 of this register are port-specific, but Byte 11( Bits 80-87) is common to all ports in the PD controller.

Table 3-9 Interrupt Clear for I2C1 Register Field Descriptions

Bit	Field	Type	Reset	Description
87-83	RESERVED	R/W	0h	Reserved
82	I2C Controller NACKed	R/W	0h
81	Ready for Patch	R/W	0h
80	Patch Loaded	R/W	0h
79	RESERVED	R/W	0h
78	RESERVED	R/W	0h
77	RESERVED	R/W	0h
76	RESERVED	R/W	0h
75	RESERVED	R/W	0h
74	RESERVED	R/W	0h
73	RESERVED	R/W	0h	Reserved
72	RESERVED	R/W	0h
71	RESERVED	R/W	0h
70	RESERVED	R/W	0h
69	RESERVED	R/W	0h
68	RESERVED	R/W	0h
67	RESERVED	R/W	0h
66	MBRD Buffer Ready	R/W	0h
65	TX Memory Buffer Empty	R/W	0h
64	RESERVED	R/W	0h
63	RESERVED	R/W	0h
62	RESERVED	R/W	0h
61	RESERVED	R/W	0h	Reserved
60	Liquid Detection	R/W	0h	Liquid Detection
59	RESERVED	R/W	0h
58	RESERVED	R/W	0h
57	Ext DCDC Source Safe State	R/W	0h
56	Ext DCDC Sink Safe State	R/W	0h
57-55	RESERVED	R/W	0h	Reserved
56-55	RESERVED	R/W	0h
56-54	RESERVED	R/W	0h	Reserved
55-54	RESERVED	R/W	0h	Reserved
53	RESERVED	R/W	0h
52	RESERVED	R/W	0h
51	RESERVED	R/W	0h
50	RESERVED	R/W	0h
49	RESERVED	R/W	0h
48	RESERVED	R/W	0h
47	RESERVED	R/W	0h	Reserved
46	Unable to Source Error	R/W	0h
45	RESERVED	R/W	0h	Reserved
44	RESERVED	R/W	0h
43	Plug Early Notification	R/W	0h
42	Sink Transition Completed	R/W	0h
41	RESERVED	R/W	0h
40	RESERVED	R/W	0h	Reserved
39	Message Data Error	R/W	0h
38	Protocol Error	R/W	0h
37	RESERVED	R/W	0h	Reserved
36	Missing Get Capabilities Message Error	R/W	0h
35	Power Event Occurred Error	R/W	0h
34	Can Provide Voltage or Current Later Error	R/W	0h
33	Cannot Provide Voltage or Current Error	R/W	0h
32	Device Incompatible Error	R/W	0h
31	RESERVED	R/W	0h
30	CMD1 Complete	R/W	0h
29-28	RESERVED	R/W	0h	Reserved
27	PD Status Updated	R/W	0h
26	Status Updated	R/W	0h
25	RESERVED	R/W	0h
24	Power Status Updated	R/W	0h
23	Power Path Switch Changed	R/W	0h
22	RESERVED	R/W	0h	Reserved
21	USB Host No Longer Present	R/W	0h
20	USB Host Present	R/W	0h
19	RESERVED	R/W	0h	Reserved
18	Data Swap Requested	R/W	0h
17	Power Swap Requested	R/W	0h
16-15	RESERVED	R/W	0h	Reserved
14	Source Cap Message Received	R/W	0h
13	New Contract as Provider	R/W	0h
12	New Contract as Consumer	R/W	0h
11	RESERVED	R/W	0h
10	RESERVED	R/W	0h
9	Overcurrent	R/W	0h
8-7	RESERVED	R/W	0h	Reserved
6	RESERVED	R/W	0h
5	Data Swap Complete	R/W	0h
4	Power Swap Complete	R/W	0h
3	Plug Insert or Removal	R/W	0h
2	RESERVED	R/W	0h	Reserved
1	PD Hardreset	R/W	0h
0	RESERVED	R/W	0h	Reserved

3.8 Status Register (Offset = 1Ah) [Reset = 0000000000h]

Status is shown in Table 3-10.

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Status bit field for non-interrupt events.

Table 3-10 Status Register Field Descriptions

Bit	Field	Type	Reset	Description
39-34	RESERVED	R	0h	Reserved
33-32	RESERVED	R	0h	Reserved
31	RESERVED	R	0h	Reserved
30	SOC Ack Timeout	R	0h	Indicates whether the attached SoC has responded timely. 0h = SoC has responded timely 1h = SoC has not responded timely
29-28	RESERVED	R	0h	Reserved
27	BIST	R	0h	Indicates if a BIST procedure is in progress. 0h = No BIST in progress 1h = BIST in progress
26	RESERVED	R	0h	Reserved
25-24	Acting as Legacy	R	0h	Indicates when PD Controller has gone into a mode where it is acting like a legacy (non PD) device. It can take approximately 10 seconds for the PD controller to determine that it is attached to a legacy source or sink. 0h = PD Controller is not in a legacy (non PD) mode 1h = PD Controller is acting like a legacy sink 2h = PD Controller is acting like a legacy source 3h = Acting as legacy sink due to dead-battery.
23-22	USB Host Present	R	0h	USB host attachment status. 0h = No host present 1h = Attached source is not data capable 2h = Attached source is not USB PD capable 3h = Host present
21-20	VBUS Status	R	0h	Indicates the present state of VBUS. 0h = At vSafe0V (less than 0.8V) 1h = At vSafe5V (4.75V to 5.5V) 2h = Within expected limits 3h = Not within any of the other specified ranges
19-7	RESERVED	R	0h	Reserved
6	Data Role	R	0h	PD controller data role. This is only valid once there is a connection. 0h = Upward-facing port (UFP) 1h = Downward-facing port (DFP)
5	Port Role	R	0h	Current state of PD Controller CCx terminations. This also indicates the PD Controller Power Role, once connected. This bit does not toggle during Unattached.* state transitions. 0h = PD Controller is in the Sink role 1h = PD Controller is Source (CCx pull-up active)
4	Plug Orientation	R	0h	Plug orientation indicator. Indicates port orientation when known (requires connection). 0h = Upside-up orientation (plug CC on CC1) 1h = Upside-down orientation (plug CC on CC2)
3-1	Connection State	R	0h	Details of a connected plug. 0h = No connection 1h = Port is disabled 2h = Audio connection (Ra/Ra) 3h = Debug connection (Rd/Rd) 4h = No connection Ra detected (Ra but no Rd) 5h = Reserved (may be used for Rp/Rp Debug connection) 6h = Connection present no Ra detected 7h = Connection present Ra detected
0	Plug Present	R	0h	Status of the plug 0h = No plug is connected 1h = A plug is connected

3.9 Power Path Status Register (Offset = 26h) [Reset = 0000000000h]

Power Path Status is shown in Table 3-11.

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Power Path Status.

Table 3-11 Power Path Status Register Field Descriptions

Bit	Field	Type	Reset	Description
39-38	Power Source	R	0h	Indicates current PD Controller power source. NOTE: Since the Dead Battery flag forces PD Controller to be powered from VBUS, only 10b is valid when this flag is set. Any other setting indicates that the Dead Battery flag is not set. 0h = Reserved 1h = PD Controller is powered from VIN_3V3 2h = PD Controller is powered from VBUS 3h = Reserved
37-35	RESERVED	R	0h	Reserved
34	PPCable1 Overcurrent	R	0h	PP_CABLE1 overcurrent indicator. Asserted if an overcurrent condition exists on PP_CABLE1 (VCONN).
33-29	RESERVED	R	0h	Reserved
28	PP1 Overcurrent	R	0h	PP_5V1 overcurrent indicator. Asserted if an overcurrent conditions exists on PP1 switch (PP_5V1).
27-21	RESERVED	R	0h	Reserved
20-18	RESERVED	R	0h	Reserved
17-15	RESERVED	R	0h	Reserved
14-12	PP3 Switch	R	0h	Indicates current state of PP3 (PP_EXT1). 0h = PP3 switch disabled 1h = PP3 switch currently disabled due to fault 2h = PP3 switch enabled (system output) 3h = PP3 switch enabled (system input)
11-9	RESERVED	R	0h	Reserved
8-6	PP1 Switch	R	0h	Indicates current state of PP1 switch (PP_5V1). 0h = PP1 switch disabled 1h = PP1 switch currently disabled due to fault 2h = PP1 switch enabled (system output)
5-2	RESERVED	R	0h	Reserved
1-0	PPCable1 Switch	R	0h	Indicates current state of PP_CABLE1 switch. 0h = PP_CABLE1 switch disabled 1h = PP_CABLE1 switch currently disabled 2h = PP_CABLE1 switch CC1 enabled (system output) 3h = PP_CABLE1 switch CC2 enabled (system output)

3.10 Port Configuration Register (Offset = 28h) [Reset = 000000000000000000000000002F4802h]

Port Configuration is shown in Table 3-12.

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Configuration for port-specific hardware. This register configures hardware that is specific for each port and in most cases will not change in normal operation or will not require immediate action if changed. Any modifications to this register will cause a port disconnect and reconnect with the new settings. Initialized by Application Customization.

Table 3-12 Port Configuration Register Field Descriptions

Bit	Field	Type	Reset	Description
127-96	RESERVED	R/W	0h	Reserved
95-80	RESERVED	R/W	0h	Reserved
79-73	RESERVED	R/W	0h	Reserved
72	RESERVED	R/W	0h	Reserved
71-64	RESERVED	R/W	0h	Reserved
63-48	VBUS For Valid PPS Status	R/W	0h
47-32	APDO VBUS Uvp TripPoint Offset	R/W	0h
31	RESERVED	R/W	0h	Reserved
30-29	APDO ILIM Over Shoot	R/W	0h
28-27	APDO VBUS UVP Threshold	R/W	0h
26-24	VBUS Sink UVP Trip HV	R/W	0h	VBUS disconnect when power role is sink. The disconnect threshold is set to (1-VBUS_SinkUvpTripHV)*(min expected VBUS). The 000b setting follows the USB-C specification requirements. Use a non-zero value for additional margin. 0h = 5% 1h = 10% 2h = 15% 3h = 20% 4h = 25% 5h = 30% 6h = 40% 7h = 50%
23-22	RESERVED	R/W	0h	Reserved
21-20	OVP for PP5V	R/W	2h	VBUS OVP settings while sourcing from PP5V. This applies while sourcing through PP1 or PP2. See data-sheet for voltage range. 0h = Use setting 0: 5.25 V (typical) 1h = Use setting 1: 5.5 V (typical) 2h = Use setting 2: 5.8 V (typical) 3h = Use setting 3: 6.1 V (typical)
19-18	RESERVED	R/W	0h	Reserved
17-16	VBUS OVP Usage	R/W	3h	OVP configuration settings. These two bits are used to select the OVP trip-point. The PD controller automatically computes the lowest threshold that does not overlap with the expected maximum voltage (including maximum tolerance allowed by USB PD specification). The OVP trip-point will be set at the selected percentage of the computed threshold. 0h = 100% 1h = 105% 2h = 111% 3h = 114%
15	RESERVED	R/W	0h	Reserved
14-13	RESERVED	R/W	0h	Reserved
12	RESERVED	R/W	0h
11	RESERVED	R/W	0h	Reserved
10	Disable PD	R/W	0h	Assert this bit to disable USB PD.
9-8	TypeC Support Options	R/W	0h	Configuration for optional features. This register controls whether optional Type-C state machine states are supported. NOTE: These states are mutually-exclusive and these options only exist when specific Type-C state machines are used. 0h = No Type-C optional states are supported 1h = Try.SRC state is supported as a DRP 3h = Reserved
7-2	RESERVED	R/W	0h	Reserved
1-0	TypeC State machine	R/W	2h	Port Configuration. 0h = Sink state machine only 1h = Source state machine only 2h = DRP state machine 3h = Disabled

3.11 Port Control Register (Offset = 29h) [Reset = 03915052h]

Port Control is shown in Table 3-13.

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Configuration bits affecting system policy. These bits may change during normal operation and are used for controlling the respective port. The PD Controller will not take immediate action upon writing. Changes made to this register will take effect the next time the appropriate policy is invoked. Initialized by Application Customization.

Table 3-13 Port Control Register Field Descriptions

Bit	Field	Type	Reset	Description
31-30	Charger Detect Enable	R/W	0h	Configure the types of legacy chargers to detect. 0h = Do not detect any legacy chargers 1h = Detect BC 1.2 chargers 2h = Reserved do not use 3h = Detect BC 1.2 and proprietary legacy chargers
29	RESERVED	R/W	0h	Reserved
28-26	Charger Advertise Enable	R/W	0h	Configure the types of legacy chargers to emulate. 0h = Do not emulate any legacy charger 1h = BC 1.2 CDP only 2h = BC 1.2 DCP only 3h = Reserved 4h = Reserved 5h = DCP Auto 1 (2.7V and DCP) 6h = DCP Auto 2 (1.2V 2.7V and DCP) 7h = Reserved
25	RESERVED	R/W	0h	Reserved
24	Resistor 15k Present	R/W	1h	Configure D+ and D- termination. Assert this bit if there is a 15kOhm pull-down on D+ and D- (USB2.0 Host Phy pull-downs enabled). This should not be used for DCP or DCP Auto modes. 0h = System does NOT have 15 kOhm pull-down 1h = System has 15 kOhm pull-down
23	RESERVED	R/W	0h	Reserved
22	RESERVED	R/W	0h	Reserved
21	RESERVED	R/W	0h	Reserved
20	Enable Current Monitor	R/W	1h	Assert this bit to enable the current monitor (peak and average) that are read from the ADC_RESULTS register. While asserted the PD controller will remain in the active power mode.
19	Unconstrained Power	R/W	0h	External power configuration. This also sets the Unconstrained Power bit defined by USB PD. When this bit is changed from 1 to 0 the PD controller will not attempt a power role swap with the Port Partner. If a power role swap is desired the host should issue a 'SWSr' 4CC command. 0h = No external power 1h = External power present
18	RESERVED	R/W	0h	Reserved
17	RESERVED	R/W	0h	Reserved
16	RESERVED	R/W	0h	Reserved
15	Initiate Swap to DFP	R/W	0h	Configure DR_Swap to DFP initiation. If this bit is asserted, the PD Controller automatically initiates and sends DR_Swap requests to the Port Partner when appropriate if presently operating as UFP.
14	Process Swap to DFP	R/W	1h	Configure response to DR_Swap to DFP. If this bit is asserted, the PD Controller will automatically accept a DR_Swap request to become a DFP. Otherwise, the PD Controller will reject such a request.
13	Initiate Swap to UFP	R/W	0h	Configure DR_Swap to UFP initiation. If this bit is asserted, the PD Controller automatically initiates and sends DR_Swap requests to the Port Partner when appropriate if presently operating as DFP.
12	Process Swap to UFP	R/W	1h	Configure response to DR_Swap to UFP. If this bit is asserted, the PD Controller will automatically accept a DR_Swap request to become a UFP. Otherwise, the PD Controller will reject such a request.
11	RESERVED	R/W	0h	Reserved
10	RESERVED	R/W	0h	Reserved
9	RESERVED	R/W	0h	Reserved
8	RESERVED	R/W	0h	Reserved
7	Initiate Swap to Source	R/W	0h	Configure PR_Swap to source initiation. If this bit is asserted, the PD Controller automatically initiates and sends PR_Swap requests to the Port Partner when appropriate if presently operating as Sink (C/P).
6	Process Swap to Source	R/W	1h	Configure response to PR_Swap to source. If this bit is asserted, the PD Controller will automatically accept a PR_Swap request to become a Source. Otherwise, the PD Controller will reject such a request.
5	Initiate Swap to Sink	R/W	0h	Configure PR_Swap to sink initiation. If this bit is asserted, the PD Controller automatically initiates and sends PR_Swap requests to the Port Partner when appropriate if presently operating as Source (P/C).
4	Process Swap to Sink	R/W	1h	Configure response to PR_Swap to sink. If this bit is asserted, the PD Controller will automatically accept a PR_Swap request to become a Sink. Otherwise, the PD Controller will reject such a request.
3-2	RESERVED	R/W	0h	Reserved
1-0	TypeC Current	R/W	2h	Type-C Current advertisement. This setting is ignored if a Source role is not enabled and active. This setting is also ignored during an explicit USB PD contract, where the Rp value is used for collision avoidance as required by the USB PD specification. Note that when PP5V is low, the FW will only use the default Type-C current regardless of the value in this field. 0h = USB Default Current 1h = 1.5 A 2h = 3.0 A 3h = Reserved

3.12 Boot Flags Register (Offset = 2Dh) [Reset = 0000000000h]

Boot Flags is shown in Table 3-14.

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Detailed status of boot process. This register provides details on PD Controller boot flags, Customer OTP configuration, and silicon revision

Table 3-14 Boot Flags Register Field Descriptions

Bit	Field	Type	Reset	Description
39-32	Revision ID	R	0h	Revision ID for the PD controller.
31-29	Patch Config Source	R	0h	Source of patch configuration. This field indicates the source of the configuration patch that has been successfully loaded. 0h = No configuration has been loaded 4h = Reserved 5h = A configuration has been loaded from EEPROM 6h = A configuration has been loaded from I2C 7h = Reserved
28-27	RESERVED	R	0h	Reserved
26-25	RESERVED	R	0h
24	RESERVED	R	0h	Reserved
23-20	RESERVED	R	0h	Reserved
19	System TSD	R	0h	System thermal shut-down indicator. This bit is asserted if the PD controller is rebooting after the system thermal sensor caused a reset.
18	RESERVED	R	0h	Reserved
17	RESERVED	R	0h	Reserved
16-14	RESERVED	R	0h	Reserved
13	Region 1 CRC Fail	R	0h	Region 1 CRC status indicator. This bit is asserted when the CRC of data read from Region 1 of EEPROM memory failed.
12	Region 0 CRC Fail	R	0h	Region 0 CRC status indicator. This bit is asserted when the CRC of data read from Region 0 of EEPROM memory failed.
11	RESERVED	R	0h	Reserved
10	Patch Download Error	R	0h	Asserted when a patch download error occurs.
9	Region 1 EEPROM Error	R	0h	Region 1 status indicator. This bit is asserted when an error occurred attempting to read Region 1 of EEPROM memory. A retry may have been successful.
8	Region 0 EEPROM Error	R	0h	Region 0 status indicator. This bit is asserted when an error occurred attempting to read Region 0 of EEPROM memory. A retry may have been successful.
7	Region 1 Invalid	R	0h	Region 1 header status indicator. This bit is asserted when Region 1 header of the EEPROM memory was invalid.
6	Region 0 Invalid	R	0h	Region 0 header status indicator. This bit is asserted when Region 0 header of the EEPROM memory was invalid.
5	Region 1	R	0h	Region 1 attempted indicator. This bit is asserted when Region 1 of the EEPROM memory was attempted.
4	Region 0	R	0h	Region 0 attempted indicator. This bit is asserted when Region 0 of the EEPROM memory was attempted.
3	I2C EEPROM Present	R	0h	EEPROM presence indicator. This bit is asserted when an EEPROM device was discovered during boot.
2	Dead Battery Flag	R	0h	Dead Battery flag indicator. This bit is asserted when the PD Controller booted in dead-battery mode.
1	RESERVED	R	0h	Reserved
0	Patch Header Error	R	0h	Asserted when a patch bundle header errors.

3.13 Received Source Capabilities Register (Offset = 30h) [Reset = 0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000h]

Received Source Capabilities is shown in Table 3-15.

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Received Source Capabilities. This register stores latest Source Capabilities message received over BMC.

Table 3-15 Received Source Capabilities Register Field Descriptions

Bit	Field	Type	Reset	Description
423-232	RESERVED	R	0h	Reserved
231-200	Source PDO 7	R	0h	Seventh Source Capabilities PDO received
199-168	Source PDO 6	R	0h	Sixth Source Capabilities PDO received
167-136	Source PDO 5	R	0h	Fifth Source Capabilities PDO received
135-104	Source PDO 4	R	0h	Fourth Source Capabilities PDO received
103-72	Source PDO 3	R	0h	Third Source Capabilities PDO received
71-40	Source PDO 2	R	0h	Second Source Capabilities PDO received
39-8	Source PDO 1	R	0h	First Source Capabilities PDO received
7-3	RESERVED	R	0h	Reserved
2-0	Number Valid PDOs	R	0h	Number of valid PDOs in this register. Each PDO is 4 bytes. (max of 7)

3.14 Received Sink Capabilities Register (Offset = 31h) [Reset = 0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000h]

Received Sink Capabilities is shown in Table 3-16.

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Received Sink Capabilities. This register stores latest Sink Capabilities message received over BMC.

Table 3-16 Received Sink Capabilities Register Field Descriptions

Bit	Field	Type	Reset	Description
423-232	RESERVED	R	0h	Reserved
231-200	Sink PDO 7	R	0h	Seventh Sink Capabilities PDO received
199-168	Sink PDO 6	R	0h	Sixth Sink Capabilities PDO received
167-136	Sink PDO 5	R	0h	Fifth Sink Capabilities PDO received
135-104	Sink PDO 4	R	0h	Fourth Sink Capabilities PDO received
103-72	Sink PDO 3	R	0h	Third Sink Capabilities PDO received
71-40	Sink PDO 2	R	0h	Second Sink Capabilities PDO received
39-8	Sink PDO 1	R	0h	First Sink Capabilities PDO received
7-3	RESERVED	R	0h	Reserved
2-0	Number Valid PDOs	R	0h	Number of valid PDOs in this register. Each PDO is 4 bytes. (max of 7)

3.15 Transmit Source Capabilities Register (Offset = 32h) [Reset = 0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000058260C844C2AA801h]

Transmit Source Capabilities is shown in Table 3-17.

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Source Capabilities for sending. This register stores PDOs and settings for outgoing Source Capabilities PD messages. Initialized by Application Customization.

Table 3-17 Transmit Source Capabilities Register Field Descriptions

Bit	Field	Type	Reset	Description
503-485	RESERVED	R/W	0h	Reserved
484	RESERVED	R/W	0h	Reserved
483	RESERVED	R/W	0h	Reserved
482	RESERVED	R/W	0h	Reserved
481	RESERVED	R/W	0h	Reserved
480	RESERVED	R/W	0h	Reserved
479	RESERVED	R/W	0h	Reserved
478	RESERVED	R/W	0h	Reserved
477	RESERVED	R/W	0h	Reserved
476	RESERVED	R/W	0h	Reserved
475	RESERVED	R/W	0h	Reserved
474	RESERVED	R/W	0h	Reserved
473	RESERVED	R/W	0h	Reserved
472	RESERVED	R/W	0h	Reserved
471-248	RESERVED	R/W	0h	Reserved
247-216	TX Source PDO 7	R/W	0h	Seventh Source Capabilities PDO contents.
215-184	TX Source PDO 6	R/W	0h	Sixth Source Capabilities PDO contents.
183-152	TX Source PDO 5	R/W	0h	Fifth Source Capabilities PDO contents.
151-120	TX Source PDO 4	R/W	0h	Fourth Source Capabilities PDO contents.
119-88	TX Source PDO 3	R/W	0h	Third Source Capabilities PDO contents.
87-56	TX Source PDO 2	R/W	58h	Second Source Capabilities PDO contents.
55-24	TX Source PDO 1	R/W	260C844Ch	First Source Capabilities PDO contents.
23-22	RESERVED	R/W	0h	Reserved
21-20	Power Path for PDO 7	R/W	2h	Configures which PP to use for PDO7. Same format as PowerPathForPDO2.
19-18	Power Path for PDO 6	R/W	2h	Configures which PP to use for PDO6. Same format as PowerPathForPDO2.
17-16	Power Path for PDO 5	R/W	2h	Configures which PP to use for PDO5. Same format as PowerPathForPDO2.
15-14	Power Path for PDO 4	R/W	2h	Configures which PP to use for PDO4. Same format as PowerPathForPDO2.
13-12	Power Path for PDO 3	R/W	2h	Configures which PP to use for PDO3. Same format as PowerPathForPDO2.
11-10	Power Path for PDO 2	R/W	2h	Configures which PP to use for PDO2. 0h = Reserved 1h = Reserved 2h = PP_EXT1 is used for this PDO
9-8	Power Path for PDO 1	R/W	0h	Configures which PP to use for PDO1. 0h = PP_5V1 is used for this PDO 2h = PP_EXT1 is used for this PDO
7-3	RESERVED	R/W	0h	Reserved
2-0	Number Valid PDOs	R/W	1h	Number of valid PDOs in this register. Each PDO is 4 bytes. (max of 7)

3.16 Transmit Sink Capabilities Register (Offset = 33h) [Reset = 000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000091258360C839D04h]

Transmit Sink Capabilities is shown in Table 3-18.

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Sink Capabilities for sending. This register stores PDOs for outgoing Sink Capabilities USB PD messages. Initialized by Application Customization. The PD controller transmits the contents of this register as a Sink_Capabilities message after receiving a Get_Sink_Cap message unless its configuration or USB PD rules require a different response in the context. Writes to this register have no immediate effect. The PD controller updates and uses this register each time it needs to send a Sink Capabilities message. Each PDO in this TX_SINK_CAPS register follows the definition from the USB PD specification. For more details on the meaning of each field refer to the USB PD specification.

Table 3-18 Transmit Sink Capabilities Register Field Descriptions

Bit	Field	Type	Reset	Description
423-232	RESERVED	R/W	0h	Reserved
231-200	TX Sink PDO 7	R/W	0h	Seventh Sink Capabilities PDO contents.
199-168	TX Sink PDO 6	R/W	0h	Sixth Sink Capabilities PDO contents.
167-136	TX Sink PDO 5	R/W	0h	Fifth Sink Capabilities PDO contents.
135-104	TX Sink PDO 4	R/W	0h	Fourth Sink Capabilities PDO contents.
103-72	TX Sink PDO 3	R/W	0h	Third Sink Capabilities PDO contents.
71-40	TX Sink PDO 2	R/W	00091258h	Second Sink Capabilities PDO contents.
39-8	TX Sink PDO 1	R/W	360C839Dh	First Sink Capabilities PDO contents.
7-3	RESERVED	R/W	0h	Reserved
2-0	Number Valid PDOs	R/W	4h

3.17 Active PDO Contract Register (Offset = 34h) [Reset = 000000000000h]

Active PDO Contract is shown in Table 3-19.

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Power data object for active contract. This register stores PDO data for the current explicit USB PD contract, or all zeroes if no contract.

Table 3-19 Active PDO Contract Register Field Descriptions

Bit	Field	Type	Reset	Description
47-42	RESERVED	R	0h	Reserved
41-32	First PDO Control Bits	R	0h	Contains bits 29:20 of the first PDO. It does not matter which PDO was selected, this field is always drawn from the first PDO.
31-0	Active PDO	R	0h	Power data object. This field contains the contents of the PDO Requested by PD Controller as Sink and Accepted by Source, once it is Accepted by Source.

3.18 Active RDO Contract Register (Offset = 35h) [Reset = 000000000000000000000000h]

Active RDO Contract is shown in Table 3-20.

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Power data object for the active contract. This register stores the RDO of the current explicit USB PD contract, or all zeroes if no contract.

Table 3-20 Active RDO Contract Register Field Descriptions

Bit	Field	Type	Reset	Description
95-32	RESERVED	R	0h	Reserved
31-28	Object Position	R	0h	As defined by USB PD.
27	Give Back Flag	R	0h	As defined by USB PD.
26	Capability Missmatch	R	0h	As defined by USB PD.
25	USB Communication Capable	R	0h	As defined by USB PD.
24	No USB Suspend	R	0h	As defined by USB PD.
23	Unchunked Supported	R	0h	As defined by USB PD.
22-20	RESERVED	R	0h	Reserved
19-10	Operating Current	R	0h	As defined by USB PD.
9-0	Max Min Operation Current	R	0h	As defined by USB PD.

3.19 Autonegotiate Sink Register (Offset = 37h) [Reset = 00000000000000000000000000000000000191904114503Eh]

Autonegotiate Sink is shown in Table 3-21.

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Configuration for sink power negotiations. This register defines the voltage range between which the system can function properly, allowing the PD Controller to negotiate its own contracts. Initialized by Application Customization.

Table 3-21 Autonegotiate Sink Register Field Descriptions

Bit	Field	Type	Reset	Description
191-116	RESERVED	R/W	0h	Reserved
115-105	PPS Output Voltage	R/W	0h	This is the desired output voltage in 20mV units. This is inserted as-is into the Request USB PD message. Note that some PD controllers are unable to turn on the gate-drivers if VBUS less than 3.8V, check the VBUS UVLO value in the data-sheet.
104-103	RESERVED	R/W	0h	Reserved
102-96	PPS Operating Current	R/W	0h	Operation current in Sink PPS mode. This is the desired operating current in 50 mA units. This is inserted as-is into the Request USB PD message.
95-70	RESERVED	R/W	0h	Reserved
69	PPS Disable Sink Upon Non APDO Contract	R/W	0h	Sink path handling during supply type transition. If this bit is asserted and the selected supply type is NOT a PPS APDO, then the sink path is disabled before sending the Request message. The host should only assert this bit after a PPS contract has been negotiated. This bit has no effect unless PPSEnableSinkMode is asserted.
68	PPS Required Full Voltage Range	R/W	0h	Select only a source with full voltage range. If this bit is asserted, a PPS supply type is not selected unless the APDO.MinVoltage ≤ TX_SINK_CAPS.MinPpsVoltage, APDO.MaxVoltage ≥ TX_SINK_CAPS.MaxPpsVoltage, and APDO.MaxCurrent ≥ TX_SINK_CAPS.MaxPpsCurrent. This bit has no effect unless PPSEnableSinkMode is asserted.
67	PPS Source Operating Mode	R/W	0h	Selection for CV or CC mode. If this bit is set to 1, then the PD controller assumes the system is in constant voltage mode and sets the VBUS disconnect threshold accordingly. If this bit is set to 0, then the PD controller will assume the system is in current limit mode and it will lower the VBUS disconnect threshold accordingly.
66-65	PPS Request Interval	R/W	0h	Sink PPS request interval. This field sets the frequency at which the PD controller will send a new request to the source even if the host has not made any change in the request. 0h = 8 seconds 1h = 4 seconds 2h = 2 seconds 3h = 1 second
64	PPS Enable Sink Mode	R/W	0h	Enable Sink PPS mode. If this bit is asserted, then the PD controller will attempt to negotiate a PPS sink contract. PPS contracts are prioritized over any other supply type.
63-62	RESERVED	R/W	0h	Reserved
61-52	Auto Neg Capabilities Mismatch Power	R/W	0h	Capabilities Mismatch Power Threshold. If the selected PDO offers less power than what is specified in this register, then the PD controller will assert the Capability Mismatch bit in its Request message unless NoCapabilityMismatch is set to 1. (250mW per LSB)
51-42	Auto Neg Min Voltage	R/W	64h	Minimum voltage to request. During PD power contract negotiation, the PD controller will only select voltages that are greater than or equal to the value specified in this field. Not used unless AutoComputeSinkMinVoltage=0. (50mV per LSB)
41-32	Auto Neg Max Voltage	R/W	190h	Maximum voltage to request. During PD power contract negotiation, the PD controller will only select voltages that are less than or equal to the value specified in this field. Not used unless AutoComputeSinkMinVoltage=0. (50mV per LSB)
31-22	Auto Neg Sink Min Required Power	R/W	104h	Minimum operating power required by the Sink. The PD Controller will always attempt to receive this power level from the Source. (250mW per LSB) See description in AutoComputeSinkMinPower field
21-12	RESERVED	R/W	0h	Reserved
11-8	RESERVED	R/W	0h	Reserved
7	RESERVED	R/W	0h	Reserved
6	Auto Disable Sink Upon Capability Mismatch	R/W	0h	Sink path and capability mismatch settings. If this bit is asserted, then any time the implicit or explicit power contract would cause the Capability Mismatch bit to be set the PD controller will disable the sinking path. The 'SRDY' 4CC task can override and enable the sink path. However, if the contract changes after the 'SRDY' has completed, the PD controller will disable the sink path if the contract causes a capability mismatch. This bit should only be asserted if the NoCapabilityMismatch bit is set to 0.
5	Auto Compute Sink Max Voltage	R/W	1h	Configuration for maximum voltage. The PD controller can automatically compute ANMaxVoltage, or allow the host to specify it. 0h = Provided by host 1h = Computed by PD controller
4	Auto Compute Sink Min Voltage	R/W	1h	Configuration for minimum voltage. The PD controller can automatically compute ANMinVoltage, or allow the host to specify it. 0h = Provided by host 1h = Computed by PD controller
3	No Capability Mismatch	R/W	1h	Configuration for capability mismatch in RDO. There are two conditions that will trigger a capability mismatch: If the attached source does not offer a PDO whose power is greater or equal to the ANSinkCapMismatchPower field in this register. PPS is enabled in this register and the attached source did not offer a PPS PDO that matches the requirements in TX_SINK_CAPS. If either condition is true, then the PD controller will assert the capability mismatch bit in its request unless this bit is asserted. 0h = Capability mismatch enabled 1h = Capability mismatch disabled.
2	Auto Compute Sink Min Power	R/W	1h	Minimum power sink requires. The minimum sink power is the largest power reported in any valid PDO in the TX_SINK_CAPS (0x33). The power for a particular PDO from the TX_SINK_CAPS follows for each supply type: Battery Supply: OperatingPower Variable Supply: MaxVoltageOperatingCurrent Fixed Supply: VoltageOperatingCurrent. However, if the TX_SINK_CAPS register includes Battery supply type PDO(s), then ANSinkMinRequiredPower = maximum OperatingPower in a Battery supply type PDO. 0h = Provided by host 1h = Computed by PD controller
1	No USB Suspend	R/W	1h	Value used for the NoUSBSusp Flag in the RDO. This is as defined by USB PD.
0	Auto Neg RDO Priority	R/W	0h	Configuration for tie-breaker in PDO selection. The PD controller will find the set of PDOs that fulfill the voltage requirements. From that set of PDOs it will pick the one with higher power. If two acceptable PDOs have the same power, Fixed Supply Type is preferred, and then Variable Supply has second preference. If two PDOs have the same power and the same type, then this bit determines which PDO is selected. 0h = Higher voltage 1h = Lower voltage

3.20 Power Status Register (Offset = 3Fh) [Reset = 0000h]

Power Status is shown in Table 3-22.

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Details about the power of the connection. This register reports status regarding the power of the connection.

Table 3-22 Power Status Register Field Descriptions

Bit	Field	Type	Reset	Description
15-10	RESERVED	R	0h	Reserved
9-8	Charger Advertise Status	R	0h	Charger Advertise Status 0h = Charger advertise disabled or not run 1h = Charger advertisement in process 2h = Charger advertisement complete 3h = Reserved
7-4	Charger Detect Status	R	0h	0h = Charger detection disabled or not run 1h = Charger detection in progress 2h = Charger detection complete none detected 3h = Charger detection complete SDP detected 4h = Charger detection complete BC 1.2 CDP detected 5h = Charger detection complete BC 1.2 DCP detected 6h = Charger detection complete Divider1 DCP detected 7h = Charger detection complete Divider2 DCP detected 8h = Charger detection complete Divider3 DCP detected 9h = Charger detection complete 1.2V DCP detected
3-2	TypeC Current	R	0h	This field is redundant with PD_STATUS.CCPullUp in register 0x40 when SourceSink is 1b. This field is redundant with PORT_CONTROL.TypeCCurrent in register 0x29 when SourceSink is 0b. In the future, this redundant field may be removed. This field is intended for Type-C Sink operation. If the port is connected as source, the field is updated upon initial connection only. 0h = USB Default Current 1h = 1.5 A 2h = 3.0 A 3h = Explicit PD contract sets current
1	SourceSink	R	0h	Source / Sink indicator. This bit is equivalent to PresentPDRole in register 0x40. It is replicated in this register for convenience. In the future, this redundant bit may be removed. 0h = Connection requests power 1h = Connection provides power (PD Controller as sink)
0	Power Connection	R	0h	Asserted if there is a connection. This bit is asserted when PlugPresent is TRUE and ConnState is greater than 5h. So it is redundant with information from register 0x1A. It is replicated in this register for convenience. In the future this redundant bit may be removed. 0h = No connection 1h = Connection present

3.21 PD Status Register (Offset = 40h) [Reset = 00000000h]

PD Status is shown in Table 3-23.

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Status of PD and Type-C state-machine. This register contains details regarding the status of PD messages and the Type-C state machine.

Table 3-23 PD Status Register Field Descriptions

Bit	Field	Type	Reset	Description
31	RESERVED	R	0h	Reserved
30-28	RESERVED	R	0h	Reserved
27-22	RESERVED	R	0h	Reserved
21-16	Hard Reset Details	R	0h	Reason for Hard Reset 0h = Reset value no hard reset 1h = Received from Port Partner 2h = Requested by host 3h = Invalid DR_Swap request during Active Mode 4h = DischargeFailed. 5h = NoResponseTimeOut. 6h = SendSoftReset. 7h = Sink_SelectCapability. 8h = Sink_TransitionSink. 9h = Sink_WaitForCapabilities. Ah = SoftReset. Bh = SourceOnTimeout. Ch = Source_CapabilityResponse. Dh = Source_SendCapabilities. Eh = SourcingFault. Fh = UnableToSource. 10h = FRS failure 11h = Unexpected message 12h = Failure to to complete the VCONN recovery sequence within 200ms after PP5V rising edge
15-13	RESERVED	R	0h	Reserved
12-8	Soft Reset Details	R	0h	Reason for Soft Reset 0h = Reset value no soft reset 1h = Soft reset received from Port Partner 2h = Reserved 3h = Reserved 4h = Received source capabilities message was invalid 5h = Message retries were exhausted 6h = Received an accept message unexpectedly 7h = Received a control message unexpectedly 8h = Received a GetSinkCap message unexpectedly 9h = Received a GetSourceCap message unexpectedly Ah = Received a GotoMin message unexpectedly Bh = Received a PS_RDY message unexpectedly Ch = Received a Ping message unexpectedly Dh = Received a Reject message unexpectedly Eh = Received a Request message unexpectedly Fh = Received a Sink Capabilities message unexpectedly 10h = Received Source Capabilities message unexpected 11h = Received a Swap message unexpectedly 12h = Received a Wait Capabilities message unexpectedly 13h = Received an unknown control message 14h = Received an unknown data message 15h = To initialize SOP' controller in plug 16h = To initialize SOP'' controller in plug 17h = Received an Extended message unexpectedly 18h = Received an unknown Extended message 19h = Received a data message unexpectedly 1Ah = Received a Not Supported message unexpectedly 1Bh = Received a Get_Status message unexpectedly
7	RESERVED	R	0h	Reserved
6	Present PD Role	R	0h	Present PD power role. The PD Controller is acting under this PD power role. 0h = Sink 1h = Source
5-4	Port Type	R	0h	Present Type-C power role. The PD Controller is acting under this Type-C power role. 0h = Sink/Source 1h = Sink 2h = Source 3h = Source/Sink
3-2	CC Pullup	R	0h	CC Pull-up value. The pull-up value detected by PD Controller when in CC Pull-down mode. 0h = Not in CC pull-down mode / no CC pull-up detected 1h = USB Default current 2h = 1.5 A (SinkTxNG) 3h = 3.0 A (SinkTxOK)
1-0	RESERVED	R	0h	Reserved

3.22 IO Config Register (Offset = 5Ch) [Reset = 000000000000000000000000000000000000000000000000000000000000000000000000000000000000000400000014CFh]

IO Config is shown in Table 3-24.

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Application-specific GPIO Configurations. This register cannot be modified at run-time, the GPIO configurations are set according to the configuration during the boot process.

Table 3-24 IO Config Register Field Descriptions

Bit	Field	Type	Reset	Description
391-384	GPIO 12 Mapped Event	R	0h	Event table mapping for GPIO12. See GPIO Event table.
383-376	GPIO 11 Mapped Event	R	0h	Event table mapping for GPIO11. See GPIO Event table.
375-368	GPIO 10 Mapped Event	R	0h	Event table mapping for GPIO10. See GPIO Event table.
367-352	RESERVED	R	0h	Reserved
351-344	GPIO 7 Mapped Event	R	0h	Event table mapping for GPIO7. See GPIO Event table.
343-336	GPIO 6 Mapped Event	R	0h	Event table mapping for GPIO6. See GPIO Event table.
335-328	GPIO 5 Mapped Event	R	0h	Event table mapping for GPIO5. See GPIO Event table.
327-320	GPIO 4 Mapped Event	R	0h	Event table mapping for GPIO4. See GPIO Event table.
319-312	GPIO 3 Mapped Event	R	0h	Event table mapping for GPIO3. See GPIO Event table.
311-304	GPIO 2 Mapped Event	R	0h	Event table mapping for GPIO2. See GPIO Event table.
303-296	GPIO 1 Mapped Event	R	0h	Event table mapping for GPIO1. See GPIO Event table.
295-288	GPIO 0 Mapped Event	R	0h	Event table mapping for GPIO0. See GPIO Event table.
287-269	RESERVED	R	0h	Reserved
268-256	GPIO Event Polarity	R	0h	Controls polarity of a selected output event for each GPIO. Assert the bit for a given GPIO to invert the polarity of the event mapped to it. This field has no impact for input GPIO Events.
255-230	RESERVED	R	0h	Reserved
229	GPIO 5 Analog Input Control	R	0h	Assert when GPIO5 is used as an analog input. This must also be asserted when PORT_CONTROL.ChargerDetectEnable or ChargerAdvertiseEnable is non-zero.
228	GPIO 4 Analog Input Control	R	0h	Assert when GPIO4 is used as an analog input. This must also be asserted when PORT_CONTROL.ChargerDetectEnable or ChargerAdvertiseEnable is non-zero.
227	RESERVED	R	0h	Reserved
226	GPIO AI Enable GPIO 2	R	0h	Assert when GPIO4 is used as an analog input.
225	RESERVED	R	0h	Reserved
224	GPIO AI Enable GPIO 0	R	0h	Assert when GPIO4 is used as an analog input.
223-205	RESERVED	R	0h	Reserved
204-192	Internal Pull Up Enable	R	0h	Controls weak pull-up setting for each configurable GPIO (1=Enabled, 0=Disabled).
191-173	RESERVED	R	0h	Reserved
172-160	Internal Pull Down Enable	R	0h	Controls weak pull-down setting for each configurable GPIO (1=Enabled, 0=Disabled).
159-140	RESERVED	R	0h	Reserved
139-128	RESERVED	R	0h	Reserved
127-109	RESERVED	R	0h	Reserved
108-96	Open Drain Output Enable	R	0h	Controls push-pull (0) vs. open-drain (1) setting for each configurable GPIO.
95-77	RESERVED	R	0h	Reserved
76-64	Initial Value	R	0h	Controls default output level for each GPIO enabled as output (0=Drive Low, 1=Drive High)
63-45	RESERVED	R	0h	Reserved
44-32	GPIO Interrupt Enable	R	400h	Controls interrupt enable for each GPIO (1=Interrupt Enabled, 0=Interrupt Disabled). Note that all GPIO pins may not be configured as inputs (see the data-sheet).
31-13	RESERVED	R	0h	Reserved
12-0	GPIO Output Enable	R	14CFh	Controls output enable for each GPIO (1=Output Enabled, 0=Hi-Z). Note that all GPIO may not be configurable as an output (see data-sheet).

3.23 Type C State Register (Offset = 69h) [Reset = 00000000h]

Type C State is shown in Table 3-25.

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Contains current status of both CCn pins.

Table 3-25 Type C State Register Field Descriptions

Bit	Field	Type	Reset	Description
31-24	TypeC Port State	R	0h	Present state of Type-C state-machine. 0h = Disabled 5h = ErrorRecovery 24h = Unattached.Accessory 2Bh = AttachWait.Accessory 45h = Try.SRC 4Eh = TryWait.SNK 4Fh = Try.SNK 50h = TryWait.SRC 60h = Attached.SRC 61h = Attached.SNK 62h = AudioAccessory 63h = DebugAccessory 64h = AttachWait.SRC 65h = AttachWait.SNK 66h = Unattached.SNK 67h = Unattached.SRC
23-16	CC2 Pin State	R	0h	State of CC2 pin 0h = Not connected 1h = Ra detected (Source only) 2h = Rd detected (Source only) 3h = USB Default Advertisement detected (SInk only) 4h = 1.5A Advertisement detected (Sink Only) 5h = 3.0A Advertisement detected (Sink Only)
15-8	CC1 Pin State	R	0h	State of CC1 pin 0h = Not connected 1h = Ra detected (Source only) 2h = Rd detected (Source only) 3h = USB Default Advertisement detected (SInk only) 4h = 1.5A Advertisement detected (Sink Only) 5h = 3.0A Advertisement detected (Sink Only)
7-0	CC Pin for PD	R	0h	CC pin used for PD communication. 0h = Not connected 1h = CC1 is used for USB PD communication 2h = CC2 is used for USB PD communication

3.24 ADC Results Register (Offset = 6Ah) [Reset = 00000000000000000000000000h]

ADC Results is shown in Table 3-26.

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Provides access to measurements from the internal ADC. The PD controller periodically measures the pins mentioned in this register and updates the register accordingly. The frequency of the update depends upon the mode of the PD controller. For example, in Unconnected Sleep the PD controller will not update these registers.

Table 3-26 ADC Results Register Field Descriptions

Bit	Field	Type	Reset	Description
103-96	RESERVED	R	0h	Reserved
95-88	IVBUS1_Mean	R	0h	Most recent current peak estimate through PP_5V1. If PORT_CONTROL.EnableCurrentMonitor = 1, this field is an estimate of the recent mean current. It is cleared upon attach for a new connection.(16.5mA per LSB)
87-80	GPIO2	R	0h	Most recent voltage on the GPIO2 pin. (14mV per LSB)
79-72	GPIO0	R	0h	Most recent voltage on the GPIO0 pin. (14mV per LSB)
71-64	GPIO5	R	0h	Most recent voltage on the GPIO5 pin. (14mV per LSB)
63-56	GPIO4	R	0h	Most recent voltage on the GPIO4 pin. (14mV per LSB)
55-48	RESERVED	R	0h	Reserved
47-40	IVBUS1	R	0h	Most recent current measurement through PP_5V1. (16.5mA per LSB)
39-32	RESERVED	R	0h	Reserved
31-24	VBUS1	R	0h	Most recent voltage on the PA_VBUS pin. (98mV per LSB)
23-16	LDO3V3	R	0h	Most recent voltage on the LDO_3V3 pin. (14mV per LSB)
15-8	ADCIN2	R	0h	Most recent voltage on the ADCIN2 pin. (14mV per LSB)
7-0	ADCIN1	R	0h	Most recent voltage on the ADCIN1 pin. (14mV per LSB)

3.25 Sleep Control Register (Offset = 70h) [Reset = 01h]

Sleep Control Register is shown in Table 3-27.

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Sleep configurations.

Table 3-27 Sleep Control Register Field Descriptions

Bit	Field	Type	Reset	Description
7-3	RESERVED	R/W	0h	Reserved
2-1	Sleep Time	R/W	0h	Minimum time the PD controller waits before entering sleep mode. 0h = Reserved 1h = 100 ms 2h = 1200 ms 3h = Reserved
0	Sleep Mode Allowed	R/W	1h	If this bit is asserted the PD controller will enter sleep modes after device is idle for Sleep Time.

3.26 GPIO Status Register (Offset = 72h) [Reset = 0000000000000000h]

GPIO Status is shown in Table 3-28.

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Captures status and settings of all GPIO pins. Check the device-specific datasheet for the available GPIO because it may vary by device type.

Table 3-28 GPIO Status Register Field Descriptions

Bit	Field	Type	Reset	Description
63-40	RESERVED	R	0h	Reserved
39	GPIO 7 Direction	R	0h	This bit is asserted when this GPIO is configured as an output.
38	GPIO 6 Direction	R	0h	This bit is asserted when this GPIO is configured as an output.
37	GPIO 5 Direction	R	0h	This bit is asserted when this GPIO is configured as an output.
36	GPIO 4 Direction	R	0h	This bit is asserted when this GPIO is configured as an output.
35	GPIO 3 Direction	R	0h	This bit is asserted when this GPIO is configured as an output.
34	GPIO 2 Direction	R	0h	This bit is asserted when this GPIO is configured as an output.
33	GPIO 1 Direction	R	0h	This bit is asserted when this GPIO is configured as an output.
32	GPIO 0 Direction	R	0h	This bit is asserted when this GPIO is configured as an output.
31-13	RESERVED	R	0h	Reserved
12	GPIO 12 Data	R	0h	Asserted if a logic high is detected on the GPIO.
11-8	RESERVED	R	0h	Reserved
7	GPIO 7 Data	R	0h	Asserted if a logic high is detected on the GPIO.
6	GPIO 6 Data	R	0h	Asserted if a logic high is detected on the GPIO.
5	GPIO 5 Data	R	0h	Asserted if a logic high is detected on the GPIO.
4	GPIO 4 Data	R	0h	Asserted if a logic high is detected on the GPIO.
3	GPIO 3 Data	R	0h	Asserted if a logic high is detected on the GPIO.
2	GPIO 2 Data	R	0h	Asserted if a logic high is detected on the GPIO.
1	GPIO 1 Data	R	0h	Asserted if a logic high is detected on the GPIO.
0	GPIO 0 Data	R	0h	Asserted if a logic high is detected on the GPIO.

3.27 Liquid Detection Config Register (Offset = 98h) [Reset = 000000000000000000000h]

Liquid Detection Config is shown in Table 3-29.

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Liquid Detection Configuration

Table 3-29 Liquid Detection Config Register Field Descriptions

Bit	Field	Type	Reset	Description
82	Enable Liquid Detection	R/W	0h	Enables liquid detection on the SBU pins connected to the GPIO on the PD Controller. In order for this to function correctly the proper external liquid detection circuitry must be in place.
81	Enable Corrosion Mitigation	R/W	0h	Enable corrosion mitigation. Corrosion mitigation will disconnect the port, disabled the port, and pull down CC pins.
80	Liquid Detection State	R/W	0h	Liquid Detection State
79-76	Sample Time in 10ms Liquid	R/W	0h	Sample Time in multiples of 10ms (10ms per LSB as ms)
75-72	Sample Time in 10ms No Liquid	R/W	0h	Sample Time in multiples of 10ms (10ms per LSB as ms)
71-64	High Threshold ADC Liquid	R/W	0h	High Threshold ADC Liquid (14mV per LSB as mV)
63-56	Low Threshold ADC Liquid	R/W	0h	Low Threshold ADC Liquid (14mV per LSB as mV)
55-48	High Threshold ADC No Liquid	R/W	0h	High Threshold ADC No Liquid, provides hysteresis for exit out of Liquid Detected. (14mV per LSB as mV)
47-40	Low Threshold ADC No Liquid	R/W	0h	Low Threshold ADC No Liquid, provides hysteresis for exit out of Liquid Detected. (14mV per LSB as mV)
39-32	Number of Samples	R/W	0h	Number of samples (must be 2^N) to take average
31-16	Sleep Time In Sec Liquid	R/W	0h	Sleep in multiples of 1s when liquid is detected (1000ms per LSB as ms)
15-0	Sleep Time In Sec No Liquid	R/W	0h	Sleep in multiples of 1s when liquid is not detected. (1000ms per LSB as ms)