SLVUD09 January   2025 TPS65219

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1Introduction
  5. 2PDN and Sequence Diagrams
    1. 2.1 TPS6521910 Sequence and Power Block Diagram
  6. 3EEPROM Device Settings
    1. 3.1  Device ID
    2. 3.2  Enable Settings
    3. 3.3  Regulator Voltage Settings
    4. 3.4  Sequence Settings
      1. 3.4.1 Power-Up Sequence
      2. 3.4.2 Power-Down Sequence
    5. 3.5  EN / PB / VSENSE Settings
    6. 3.6  Multi-Function Pin Settings
    7. 3.7  Over-Current Deglitch
    8. 3.8  Mask Settings
    9. 3.9  Discharge Check
    10. 3.10 Multi PMIC Config
  7. 4Revision History

3.5 EN / PB / VSENSE Settings

The EN/PB/VSENSE pin is used to enable or disable the PMIC. This pin can be configured in one of three ways: EN, PB or VSENSE. The table below shows the default configuration for this pin. Please note, if the FSD (First supply detection) feature is enabled, the device goes from "No Power" to "Active" state, executing the power-up sequence as soon as the voltage on VSYS is above the POR threshold. In this scenario, the EN/PB/VSENSE pin is ignored ONLY during the first power-up.

Table 3-10 EN / PB / VSENSE Settings
Register Address Field Name Value Description
Pin Config 0x20 EN_PB_VSENSE_CONFIG 0x1 Push Button Configuration
ON Deglitch 0x20 EN_PB_VSENSE_DEGL 0x1 long (typ: 50ms for EN/VSENSE and 600ms for PB)
First Supply Detection 0x20 PU_ON_FSD 0x1 First Supply Detection (FSD) Enabled.
Note: The deglitch configured on register field "EN_PB_VSENSE_DEGL" is for the ON request. The deglitch for the OFF request is not configurable. The parameters that are not configurable can be found in the Specifications section of the device data sheet.