SNLA415 August   2022 DS160PT801

 

  1.   Abstract
  2.   Trademarks
  3. 1Introduction
  4. 2History
  5. 3Components of PCIe Communication
    1. 3.1 Root Complex
    2. 3.2 Repeater
    3. 3.3 Endpoints
  6. 4Signaling
    1. 4.1 PERST
    2. 4.2 WAKE and CLKREQ
    3. 4.3 REFCLK
  7. 5Link Training
    1. 5.1 Receiver Detect (Rx Detect)
    2. 5.2 Polling
    3. 5.3 Configuration
  8. 6Link Equalization
    1. 6.1 Phase 0 and 1
    2. 6.2 Phase 2 and 3
  9. 7Summary
  10. 8References

4.1 PERST

PERST is referred to as a fundamental reset. PERST should be held low until all the power rails in the system and the reference clock are stable. A transition from low to high in this signal usually indicates the beginning of link initialization. In Figure 4-1, it is referred as "PERST#."