SNLA425A february   2023  – june 2023 DS160PR1601 , DS320PR1601

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1Access Methods
    1. 1.1 Typical PCIe x16 Lane to DS160PR1601 and DS320PR1601 Channel Mapping
    2. 1.2 Device Configuration Through External EEPROM
  5. 2Register Mapping
    1. 2.1 Share Registers
    2. 2.2 Channel Registers
  6. 3Equalization Control Settings
  7. 4CTLE Index and Flat Gain Selection Matrix
  8. 5Programming Examples
  9. 6References
  10. 7Revision History

3 Equalization Control Settings

Table 3-1 CTLE Index Equalization Settings
Equalization Setting Typical EQ Boost (dB)
EQ Index SMBus/I2C Mode @ 8 GHz @ 16 GHz (DS320PR1601 only)
EQ Control Register Eq_stage1_3:0 EQ Control Register Eq_stage2_2:0 EQ GAIN / Flat Gain Control Register Eq_profile_3:0 EQ Control Register Eq_stage1_bypass
0 0 0 0 1 For values, see the device-specific data sheet For values, see the device-specific data sheet
1 1 0 0 1
2 3 0 0 1
Default 0 0 0 0
5 0 0 1 0
6 1 0 1 0
7 2 0 1 0
8 3 0 3 0
9 4 0 3 0
10 5 1 7 0
11 6 1 7 0
12 8 1 7 0
13 10 1 7 0
14 10 2 15 0
15 11 3 15 0
16 12 4 15 0
17 13 5 15 0
18 14 6 15 0
19 15 7 15 0