SNLA431 January   2024 DP83TC812R-Q1 , DP83TC812S-Q1

 

  1.   1
  2.   Trademarks
  3. 1Preface
  4.   Notational Conventions
  5. 2Related Documentation
  6. 3Support Resources
  7. 4Troubleshooting the PHY Application
    1. 4.1  Schematic and Layout Checklist
    2. 4.2  Verify Successful Power-up of PHY
    3. 4.3  Peripheral Pin Checks
      1. 4.3.1 Probe the RESET_N pin
      2. 4.3.2 Probe the INH pin
      3. 4.3.3 Probe the CLKOUT pin
      4. 4.3.4 Probe the Serial Management Interface (MDC, MDIO) Pins
    4. 4.4  Register Dump Comparison
    5. 4.5  Verifying Strap Configurations
    6. 4.6  Check the MDI Signal
    7. 4.7  Link Up Failed Common Issues
    8. 4.8  Signal Quality Check
    9. 4.9  Power Up Timing
    10. 4.10 Loopback Testing
    11. 4.11 Debugging the MAC Interface
    12. 4.12 Verify Open Alliance PMA Compliance
    13. 4.13 Tools and References
      1. 4.13.1 DP83TC812 Register Access
      2. 4.13.2 DP83TC812 USB2MDIO Scripts
      3. 4.13.3 Extended Register Access
      4. 4.13.4 Software and Driver Debug on Linux
        1. 4.13.4.1 Commonly Seen Linux Terminal Outputs
  8. 5Conclusion

1 Preface

The DP83TC812-Q1 device is an IEEE 802.3bw compliant automotive Ethernet physical layer transceiver which operates with Single Twisted Pair cable. The PHY supports TC10 sleep and wake features and provides all physical layer functions needed to transmit and receive data over unshielded or shielded single twisted-pair cables. The device provides xMII flexibility with support for standard MII, RMII, RGMII, and SGMII MAC interfaces. The PHY also integrates a low pass filter on the MDI side to reduce emissions.

Figure 1-1 shows a high-level system block diagram of a typical DP83TC812 application.

GUID-BFDE4FA3-B7DA-41AB-8168-0DB6A9C3FA0C-low.gifFigure 1-1 DP83TC812 Block Diagram