SNLS488 March   2016 DS90UB921-Q1

PRODUCTION DATA.  

  1. Features
  2. Applications
  3. Description
  4. Revision History
  5. Pin Configuration and Functions
  6. Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings - JEDEC
    3. 6.3  ESD Ratings—IEC and ISO
    4. 6.4  Recommended Operating Conditions
    5. 6.5  Thermal Information
    6. 6.6  DC Electrical Characteristics
    7. 6.7  AC Electrical Characteristics
    8. 6.8  PCLK Timing Requirements
    9. 6.9  Recommended Timing for the Serial Control Bus
    10. 6.10 Switching Characteristics
    11. 6.11 Typical Charateristics
  7. Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  High Speed Forward Channel Data Transfer
      2. 7.3.2  Low Speed Back Channel Data Transfer
      3. 7.3.3  Common Mode Filter Pin (CMF)
      4. 7.3.4  Video Control Signal Filter
      5. 7.3.5  EMI Reduction Features
        1. 7.3.5.1 Input SSC Tolerance (SSCT)
      6. 7.3.6  LVCMOS VDDIO Option
      7. 7.3.7  Power Down (PDB)
      8. 7.3.8  Remote Auto Power-Down Mode
      9. 7.3.9  Input PCLK Loss Detect
      10. 7.3.10 Serial Link Fault Detect
      11. 7.3.11 Pixel Clock Edge Select (TRFB)
      12. 7.3.12 Frequency Mode Optimizations
      13. 7.3.13 Interrupt Pins - Funtional Description and Usage (INTB, REM_INTB)
      14. 7.3.14 Internal Pattern Generation
      15. 7.3.15 GPIO[3:0] and GPO_REG[7:4]
        1. 7.3.15.1 GPIO[3:0] Enable Sequence
        2. 7.3.15.2 GPO_REG[7:4] Enable Sequence
      16. 7.3.16 I2S Transmitting
      17. 7.3.17 Built In Self Test (BIST)
        1. 7.3.17.1 BIST Configuration and Status
          1. 7.3.17.1.1 Sample BIST Sequence
        2. 7.3.17.2 Forward Channel And Back Channel Error Checking
    4. 7.4 Device Functional Modes
      1. 7.4.1 Configuration Select (MODE_SEL)
      2. 7.4.2 Repeater Application
        1. 7.4.2.1 Repeater Configuration
        2. 7.4.2.2 Repeater Connections
    5. 7.5 Programming
    6. 7.6 Register Maps
  8. Application and Implementation
    1. 8.1 Application Information
    2. 8.2 AVMUTE Operation
    3. 8.3 Typical Application
      1. 8.3.1 Design Requirements
      2. 8.3.2 Detailed Design Procedure
      3. 8.3.3 Application Curves
  9. Power Supply Recommendations
    1. 9.1 Power Up Requirements and PDB Pin
    2. 9.2 CML Interconnect Guidelines
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Documentation Support
      1. 11.1.1 Related Documentation
    2. 11.2 Community Resources
    3. 11.3 Trademarks
    4. 11.4 Electrostatic Discharge Caution
    5. 11.5 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

7 Detailed Description

7.1 Overview

The DS90UB921-Q1 serializer transmits a 35-bit symbol over a single serial FPD-Link III channel operating up to 3.36 Gbps line rate. The serial stream contains an embedded clock, video control signals and DC-balanced video data and audio data which enhance signal quality to support AC coupling. The serializer is intended for use with the DS90UB926Q-Q1, DS90UB928Q-Q1, DS90UB948-Q1, or DS90UB940-Q1 deserializers.

The DS90UB921-Q1 serializer and compatible deserializer incorporate an I2C compatible interface. The I2C compatible interface allows programming of serializer or deserializer devices from a local host controller. In addition, the devices incorporate a bidirectional control channel (BCC) that allows communication between serializer/deserializer as well as remote I2C slave devices.

The bidirectional control channel is implemented via embedded signaling in the high-speed forward channel (serializer to deserializer) as well as lower speed signaling in the reverse channel (deserializer to serializer). Through this interface, the BCC provides a mechanism to bridge I2C transactions across the serial link from one I2C bus to another. The implementation allows for arbitration with other I2C compatible masters at either side of the serial link.

There are two operating modes available on DS90UB921-Q1, display mode and camera mode. In display mode, I2C transactions originate from the host controller attached to the serializer and target either the deserializer or an I2C slave attached to the deserializer. Transactions are detected by the I2C slave in the serializer and forwarded to the I2C master in the deserializer. Similarly, in camera mode, I2C transactions originate from a controller attached to the deserializer and target either the serializer or an I2C slave attached to the serializer. Transactions are detected by the I2C slave in the deserializer and forwarded to the I2C master in the serializer.

7.2 Functional Block Diagram

DS90UB921-Q1 921block.gif

7.3 Feature Description

7.3.1 High Speed Forward Channel Data Transfer

The High Speed Forward Channel (HS_FC) is composed of 35 bits of data containing DIN[23:0] or RGB[7:0] or YUV data, sync signals, I2C, and I2S audio transmitted from Serializer to Deserializer. Figure 13 illustrates the serial stream per PCLK cycle. This data payload is optimized for signal transmission over an AC coupled link. Data is randomized, balanced and scrambled.

DS90UB921-Q1 30143337.gif Figure 13. FPD-Link III Serial Stream

The device supports clocks in the range of 5 MHz to 96 MHz. The actual line rate is 3.36 Gbps maximum and 525 Mbps Minimum.

7.3.2 Low Speed Back Channel Data Transfer

The Low-Speed Backward Channel (LS_BC) of the DS90UB921-Q1 provides bidirectional communication between the display and host processor. The information is carried back from the Deserializer to the Serializer per serial symbol. The back channel control data is transferred over the single serial link along with the high-speed forward data, DC balance coding and embedded clock information. This architecture provides a backward path across the serial link together with a high speed forward channel. The back channel contains the I2C, CRC and 4 bits of standard GPIO information with 3.1 Mbps line rate in Coax mode and low frequency STP mode, and 4.4Mbps line rate in high frequency STP mode. The back channel data rate is configured automatically when STP or Coax is selected (see Frequency Mode Optimizations).

7.3.3 Common Mode Filter Pin (CMF)

The serializer provides access to the center tap of the internal termination. A capacitor must be placed on this pin for additional common-mode filtering of the differential pair. This can be useful in high noise environments for additional noise rejection capability. A 0.1 μF capacitor must be connected to this pin to Ground.

7.3.4 Video Control Signal Filter

When operating the devices in Normal Mode, the Video Control Signals (DE, HS, VS) have the following restrictions:

  • Normal Mode with Control Signal Filter Enabled: DE and HS — Only 2 transitions per 130 clock cycles are transmitted, the transition pulse must be 3 PCLK or longer.
  • Normal Mode with Control Signal Filter Disabled: DE and HS — Only 2 transitions per 130 clock cycles are transmitted, no restriction on minimum transition pulse.
  • VS — Only 1 transition per 130 clock cycles are transmitted, minimum pulse width is 130 clock cycles.

Video Control Signals are defined as low frequency signals with limited transitions. Glitches of a control signal can cause a visual display error. This feature allows for the chipset to validate and filter out any high frequency noise on the control signals. See Figure 14.

DS90UB921-Q1 30143302.gif Figure 14. Video Control Signal Filter Waveform

7.3.5 EMI Reduction Features

7.3.5.1 Input SSC Tolerance (SSCT)

The DS90UB921-Q1 serializer is capable of tracking a triangular input spread spectrum clocking (SSC) profile up to ±2.5% amplitude deviations (center spread), up to 35 kHz modulation at 5–96 MHz, from a host source.

7.3.6 LVCMOS VDDIO Option

1.8 V or 3.3 V Inputs and Outputs are powered from a separate VDDIO supply to offer compatibility with external system interface signals.

NOTE

When configuring the VDDIO power supplies, all the single-ended data and control input pins for device need to scale together with the same operating VDDIO levels.

7.3.7 Power Down (PDB)

The Serializer has a PDB input pin to ENABLE or POWER DOWN the device. This pin can be controlled by the host or through the VDDIO, where VDDIO = 3.0V to 3.6V or VDD33. To save power disable the link when the display is not needed (PDB = LOW). When the pin is driven by the host, make sure to release it after VDD33 and VDDIO have reached final levels; no external components are required. In the case of driven by the VDDIO = 3.0V to 3.6V or VDD33 directly, a 10 kohm resistor to the VDDIO = 3.0V to 3.6V or VDD33 , and a >10uF capacitor to the ground are required (See Figure 26).

7.3.8 Remote Auto Power-Down Mode

The DS90UB921-Q1 serializer features a Remote Auto Power Down mode. This feature is enabled and disabled through the register bit 0x01[7] (Table 7). When the back channel is not detected, either due to an idle or powered-down deserializer, the serializer enters remote auto power down mode. Power dissipation of the serializer is significantly reduced in this mode. The serializer automatically attempts to resume normal operation upon detection of an active back channel from the deserializer. To complete the wake-up process and reactivate forward channel operation, the remote power-down feature must be disabled by either a local I2C host, or by an auto-ACK I2C transaction from a remote I2C host located at the deserializer. The Remote Auto Power Down Sleep/Wake cycle is shown below in Figure 15:

DS90UB921-Q1 30193309.gif Figure 15. Remote Auto Power Down Sleep/Wake Cycle

To resume normal operation, the Remote Auto Power Down feature must be disabled in the device control register. This may be accomplished from a local I2C controller by writing reg_0x01[7]=0 (Table 7). To disable from a remote I2C controller located at the deserializer, perform the following procedure to complete the wake-up process:

  1. Power up remote deserializer (back channel must be active)
  2. Enable I2C PASS-THROUGH ALL by setting deserializer register reg_0x05[7]=1
  3. Enable I2C AUTO ACK by setting deserializer register reg_0x03[2]=1
  4. Disable Remote Auto Power Down by setting serializer register reg_0x01[7]=0
  5. Disable I2C AUTO ACK by setting deserializer register reg_0x03[2]=0
  6. Disable I2C PASS-THROUGH ALL by setting deserializer register reg_0x05[7]=0

7.3.9 Input PCLK Loss Detect

The serializer can be programmed to enter a low power SLEEP state when the input clock (PCLK) is lost. This is done via register 0x03[1] (see Table 7). A clock loss condition is detected when PCLK drops below approximately 1MHz. When a PCLK is detected again, the serializer will then lock to the incoming PCLK. Note – when PCLK is lost, the Serial Control Bus Registers values are still RETAINED.

7.3.10 Serial Link Fault Detect

The serial link fault detection is able to detect any of following seven (7) conditions:

  1. cable open
  2. “+” to “-“ short
  3. “+” short to GND
  4. “-“ short to GND
  5. “+” short to battery
  6. “-“ short to battery
  7. Cable is linked correctly

If any one of the fault conditions (first 6 conditions above) occurs, The Link Detect Status is 0 (cable is not detected) on bit 0 of address 0x0C Table 7.

7.3.11 Pixel Clock Edge Select (TRFB)

The TRFB control register bit selects which edge of the Pixel Clock is used. For the serializer, this pin determines the edge that the data is latched on. If TRFB is HIGH (‘1’), data is latched on the Rising edge of the PCLK. If TRFB is LOW (‘0’), data is latched on the Falling edge of the PCLK.

7.3.12 Frequency Mode Optimizations

HFMODE, LFMODE, and IFMODE are set through a combination of the FSEL pin and MODE_SEL pin, with register overrides for both. These pins (or register overrides) will configure the DS90UB921-Q1 into either Low Frequency Mode (LFMODE), Intermediate Frequency mode (IFMODE), or High Frequency mode (HFMODE). See Table 1 for details on how each mode is enabled.

Table 1. HFMODE / LFMODE / IFMODE Configuration Table

FSEL (pin 15, or register 0x35[7:6]) ALTERNATE FREQUENCY (set by MODE_SEL pin, or register 0x04[1:0]) MODE PCLK RANGE for COAX PCLK RANGE for STP
L L HFMODE N/A 15 - 96 MHz
H L HFMODE 48 - 96 MHz N/A
H H IFMODE 24 - 48 MHz N/A
L H LFMODE 15 - 24 MHz 5 - 15 MHz

7.3.13 Interrupt Pins – Funtional Description and Usage (INTB, REM_INTB)

The REM_INTB pin mirrors the status of INTB_IN from the remote deserializer. Any change in INTB_IN status of the remote device will be reflected at the REM_INTB output of the serializer. REM_INTB will remain LOW until lock is achieved with the downstream deserializer. Alternately, the INTB pin can be set to trigger on remote interrupts by following the steps below.

  1. On DS90UB921-Q1, read register 0xC7.
  2. On DS90UB921-Q1, set register 0xC6[5] = 1 and 0xC6[0] = 1
  3. Deserializer INTB_IN is set LOW by some downstream device.
  4. DS90UB921-Q1 serializer pulls INTB (pin 31) LOW. The signal is active low, so a LOW indicates an interrupt condition.
  5. External controller detects INTB = LOW; to determine interrupt source, read ISR register 0xC7.
  6. A read to ISR will clear the interrupt at the DS90UB921-Q1, releasing INTB.
  7. The external controller typically must then access the remote device to determine downstream interrupt source and clear the interrupt driving INTB_IN. This would be when the downstream device releases the INTB_IN on the deserializer. The system is now ready to return to step (1) at next falling edge of INTB_IN.

If using the REM_INTB pin instead of INTB for remote interrupts, the IS_RX_INT bit (0xC6[5]) of the serializer's ICR register must be set low (default) masking remote interrupts to the INTB pin.

7.3.14 Internal Pattern Generation

The DS90UB921-Q1 serializer supports the internal pattern generation feature. It allows basic testing and debugging of an integrated panel through the FPD-Link III output stream. The test patterns are simple and repetitive and allow for a quick visual verification of panel operation. As long as the device is not in power down mode, the test pattern will be displayed even if no parallel input is applied. If no PCLK is received, the test pattern can be configured to use a programmed oscillator frequency. For detailed information, refer to Application Note AN-2198 (SNLA132).

7.3.15 GPIO[3:0] and GPO_REG[7:4]

In 18-bit RGB operation mode, the optional R[1:0] and G[1:0] of the DS90UB921-Q1 can be used as the general purpose IOs GPIO[3:0] in either forward channel (Inputs) or back channel (Outputs) applications.

7.3.15.1 GPIO[3:0] Enable Sequence

See Table 2 for the GPIO enable sequencing.

Step 1: Enable the 18-bit mode either through the configuration register bit Table 7 on DS90UB921-Q1 only. The deserializer is automatically configured as in the 18-bit mode.

Step 2: To enable GPIO3 forward channel, write 0x03 to address 0x0F on DS90UB921-Q1, then write 0x05 to address 0x1F on the deserializer.

Table 2. GPIO Enable Sequencing Table

# DESCRIPTION DEVICE FORWARD CHANNEL BACK CHANNEL
1 Enable 18-bit mode DS90UB921-Q1 0x12 = 0x04 0x12 = 0x04
DS90UB926Q-Q1 Auto Load from DS90UB921-Q1 Auto Load from DS90UB921-Q1
2 GPIO3 DS90UB921-Q1 0x0F = 0x03 0x0F = 0x05
DS90UB926Q-Q1 0x1F = 0x05 0x1F = 0x03
3 GPIO2 DS90UB921-Q1 0x0E = 0x30 0x0E = 0x50
DS90UB926Q-Q1 0x1E = 0x50 0x1E = 0x30
4 GPIO1 DS90UB921-Q1 0x0E = 0x03 0x0E = 0x05
DS90UB926Q-Q1 0x1E = 0x05 0x1E = 0x03
5 GPIO0 DS90UB921-Q1 0x0D = 0x93 0x0D = 0x95
DS90UB926Q-Q1 0x1D = 0x95 0x1D = 0x93

Note: GPO_REG4 of the DS90UB921-Q1 can be used as a forward channel GPIO, outputting on GPIO0 of DS90UB928Q-Q1. This is configured as follows:

  • Set DS90UB921-Q1 in 18-bit mode by register 0x12[2] = 1.
  • Set DS90UB928Q-Q1 register 0x1D[0] = 1 and 0x1D[2] = 1; this enables GPIO0 of DS90UB928Q-Q1 as an output.
  • Set DS90UB921-Q1 register 0x0F[4] = 1 and 0x0F[5] = 1; this enables GPO_REG4 of DS90UB921-Q1 as an input.

Similarly GPO_REG5 of DS90UB921-Q1 can output to GPIO1 of DS90UB928Q-Q1:

  • Set DS90UB921-Q1 in 18-bit mode by register 0x12[2] = 1.
  • Set DS90UB928Q-Q1 register 0x1E[0] = 1 and 0x1E[2] = 1; this enables GPIO1 of DS90UB928Q-Q1 as an output.
  • Set DS90UB921-Q1 register 0x10[0] = 1 and 0x10[1] = 1; this enables GPO_REG5 DS90UB921-Q1 as an input.

7.3.15.2 GPO_REG[7:4] Enable Sequence

GPO_REG[7:4] are the outputs only pins. They must be programmed through the local register bits. See Table 3 for the GPO_REG enable sequencing.

Step 1: Enable the 18-bit mode either through the configuration register bit Table 7 on DS90UB921-Q1 only. The deserializer is automatically configured as in the 18-bit mode.

Step 2: To enable GPO_REG7 outputs an “1”, write 0x09 to address 0x11 on DS90UB921-Q1.

Table 3. GPO_REG Enable Sequencing Table

# DESCRIPTION DEVICE LOCAL ACCESS LOCAL OUTPUT
1 Enable 18-bit mode DS90UB921-Q1 0x12 = 0x04
2 GPO_REG7 DS90UB921-Q1 0x11 = 0x09 “1”
0x11 = 0x01 “0”
3 GPO_REG6 DS90UB921-Q1 0x10 = 0x90 “1”
0x10 = 0x10 “0”
4 GPO_REG5 DS90UB921-Q1 0x10 = 0x09 “1”
0x10 = 0x01 “0”
5 GPO_REG4 DS90UB921-Q1 0x0F = 0x90 “1”
0x0F = 0x10 “0”

7.3.16 I2S Transmitting

In normal 24-bit RGB operation mode, the DS90UB921-Q1 supports 3 bits of I2S. They are I2S_CLK, I2S_WC and I2S_DA. The optionally packetized audio information can be transmitted during the video blanking (data island transport) or during active video (forward channel frame transport). Note: The bit rates of any I2S bits must maintain one fourth of the PCLK rate. Table 4 covers the range of I2S sample rates.

Table 4. Audio Interface Frequencies

SAMPLE RATE (kHz) I2S DATA WORD SIZE (BITS) I2S CLK (MHz)
32 16 1.024
44.1 16 1.411
48 16 1.536
96 16 3.072
192 16 6.144
32 24 1.536
44.1 24 2.117
48 24 2.304
96 24 4.608
192 24 9.216
32 32 2.048
44.1 32 2.822
48 32 3.072
96 32 6.144
192 32 12.288

7.3.17 Built In Self Test (BIST)

An optional At-Speed Built In Self Test (BIST) feature supports the testing of the high speed serial link and the low- speed back channel. This is useful in the prototype stage, equipment production, in-system test and also for system diagnostics.

7.3.17.1 BIST Configuration and Status

The BIST mode is enabled at the deseralizer by the Pin select (BISTEN and BISTC) or configuration register (Table 7) through the deserializer. When LFMODE = 0, the pin based configuration defaults to external PCLK or 33 MHz internal Oscillator clock (OSC) frequency. In the absence of PCLK, the user can select the desired OSC frequency (default 33 MHz or 25MHz) through the register bit. When LFMODE = 1, the pin based configuration defaults to external PCLK or 12.5MHz MHz internal Oscillator clock (OSC) frequency.

When BISTEN of the deserializer is high, the BIST mode enable information is sent to the serializer through the Back Channel. The serializer outputs a test pattern and drives the link at speed. The deserializer detects the test pattern and monitors it for errors. The PASS output pin toggles to flag any payloads that are received with 1 to 35 bit errors.

The BIST status is monitored real time on PASS pin. The result of the test is held on the PASS output until reset (new BIST test or Power Down). A high on PASS indicates NO ERRORS were detected. A Low on PASS indicates one or more errors were detected. The duration of the test is controlled by the pulse width applied to the deserializer BISTEN pin. This BIST feature also contains a Link Error Count and a Lock Status. If the connection of the serial link is broken, then the link error count is shown in the register. When the PLL of the deserializer is locked or unlocked, the lock status can be read in the register. See Table 7.

7.3.17.1.1 Sample BIST Sequence

See Figure 16 for the BIST mode flow diagram.

Step 1: BIST Mode is enabled via the BISTEN pin of the deserializer. The desired clock source is selected through BISTC pin.

Step 2: The DS90UB921-Q1 serializer is woken up through the back channel if it is not already on. The all zero pattern on the data pins is sent through the FPD-Link III to the deserializer. Once the serializer and the deserializer are in BIST mode and the deserializer acquires Lock, the PASS pin of the deserializer goes high and BIST starts checking the data stream. If an error in the payload (1 to 35) is detected, the PASS pin will switch low for one half of the clock period. During the BIST test, the PASS output can be monitored and counted to determine the payload error rate.

Step 3: To Stop the BIST mode, the deserializer BISTEN pin is set Low. The deserializer stops checking the data. The final test result is held on the PASS pin. If the test ran error free, the PASS output will be High. If there was one or more errors detected, the PASS output will be Low. The PASS output state is held until a new BIST is run, the device is RESET, or Powered Down. The BIST duration is user controlled by the duration of the BISTEN signal.

Step 4: The Link returns to normal operation after the deserializer BISTEN pin is low. Figure 17 shows the waveform diagram of a typical BIST test for two cases. Case 1 is error free, and Case 2 shows one with multiple errors. In most cases it is difficult to generate errors due to the robustness of the link (differential data transmission etc.), thus they may be introduced by greatly extending the cable length, faulting the interconnect, reducing signal condition enhancements (Rx Equalization).

DS90UB921-Q1 30143343.gif Figure 16. Bist Mode Flow Diagram

7.3.17.2 Forward Channel And Back Channel Error Checking

While in BIST mode, the serializer stops sampling RGB input pins and switches over to an internal all-zero pattern. The internal all-zeroes pattern goes through scrambler, dc-balancing etc. and goes over the serial link to the deserializer. The deserializer on locking to the serial stream compares the recovered serial stream with all-zeroes and records any errors in status registers and dynamically indicates the status on PASS pin. The deserializer then outputs a simultaneous switching output (SSO) pattern on the RGB output pins.

The back-channel data is checked for CRC errors once the serializer locks onto back-channel serial stream as indicated by link detect status (register bit 0x0C[0]). The CRC errors are recorded in an 8-bit register. The register is cleared when the serializer enters the BIST mode. As soon as the serializer exits BIST mode, the functional mode CRC register starts recording the CRC errors. The BIST mode CRC error register is active in BIST mode only and keeps the record of last BIST run until cleared or enters BIST mode again.

DS90UB921-Q1 30143364.gif Figure 17. Bist Waveforms

7.4 Device Functional Modes

7.4.1 Configuration Select (MODE_SEL)

Configuration of the device may be done via the MODE_SEL input pin, or via the configuration register bit. A pull-up resistor and a pull-down resistor of suggested values may be used to set the voltage ratio of the MODE_SEL input (VR4) and VDD33 to select one of the other 7 possible selected modes. The voltage range in between the Minimum and Maximum VR4 must be adhered even when taking resistor tolerances into account. The 1% suggested resistors meet this for all cases, but others that also meet the desired voltage range are also acceptable. See Figure 18 and Table 5.

DS90UB921-Q1 30143341.gif Figure 18. MODE_SEL Connection Diagram

Table 5. Configuration Select (MODE_SEL)

# MINIMUM
VR4 (V)(1)
MAXIMUM
VR4 (V)(1)
SUGGESTED RESISTOR R3 kΩ (1% tol) SUGGESTED RESISTOR R4 kΩ (1% tol) ALTERNATE FREQUENCY REPEATER 18–BIT MODE
1 0.000 0.150 Open 40.2 or Any L L L
2 0.530 0.596 90.9 18.7 L H L
3 0.725 0.800 93.1 28.0 L H H
4 0.930 1.012 71.5 30.1 H L L
5 1.165 1.284 68.1 40.2 H L H
6 1.480 1.599 82.5 71.5 H H L
7 1.750 1.905 73.2 90.9 H H H
Alternate Frequency:
 See Frequency Mode Optimizations
Repeater:
 L = Repeater OFF (Default)
 H = Repeater ON
18-bit Mode:
 L = Normal 24-bit RGB Mode (Default)
 H = 18-bit RGB Mode. Note: use of GPIO(s) on unused inputs must be enabled by register.
(1) Voltage indicated assumes nominal VDD33.

7.4.2 Repeater Application

The DS90UB921-Q1 and DS90UB926Q-Q1 can be configured to extend data transmission over multiple links to multiple display devices. Setting the devices into repeater mode provides a mechanism for transmitting to all receivers in the system.

7.4.2.1 Repeater Configuration

In the repeater application, in this document, the DS90UB921-Q1 is referred to as the Transmitter or transmit port (TX), and the DS90UB926Q-Q1 is referred to as the Receiver (RX). Figure 19 shows the maximum configuration supported for Repeater implementations using the DS90UB921-Q1 (TX) and DS90UB926Q-Q1 (RX). Two levels of Repeaters are supported with a maximum of three Transmitters per Receiver.

DS90UB921-Q1 30143310.gif Figure 19. Maximum Repeater Application

In a repeater application, the I2C interface at each TX and RX may be configured to transparently pass I2C communications upstream or downstream to any I2C device within the system. This includes a mechanism for assigning alternate IDs (Slave Aliases) to downstream devices in the case of duplicate addresses.

At each repeater node, the parallel LVCMOS interface fans out to up to three serializer devices, providing parallel RGB video data, HS/VS/DE control signals and, optionally, packetized audio data (transported during video blanking intervals). Alternatively, the I2S audio interface may be used to transport digital audio data between receiver and transmitters in place of packetized audio. All audio and video data is transmitted at the output of the Receiver and is received by the Transmitter.

Figure 20 provides more detailed block diagram of a 1:2 repeater configuration.

DS90UB921-Q1 921-922repeaterblock.gif Figure 20. 1:2 Repeater Configuration

7.4.2.2 Repeater Connections

The Repeater requires the following connections between the Receiver and each Transmitter Figure 21.

  1. Video Data – Connect PCLK, RGB and control signals (DE, VS, HS).
  2. I2C – Connect SCL and SDA signals. Both signals should be pulled up to VDD33 with 4.7 kΩ resistors.
  3. Audio – Connect I2S_CLK, I2S_WC, and I2S_DA signals.
  4. IDx pin – Each Transmitter and Receiver must have an unique I2C address.
  5. MODE_SEL pin – All Transmitter and Receiver must be set into the Repeater Mode.
  6. Interrupt pin – Connect DS90UB926Q-Q1 INTB_IN pin to DS90UB921-Q1 INTB pin. The signal must be pulled up to VDDIO.
DS90UB921-Q1 921-922repeaterdiagram.gif Figure 21. Repeater Connection Diagram

7.5 Programming

The DS90UB921-Q1 is configured by the use of a serial control bus that is I2C protocol compatible. Multiple serializer devices may share the serial control bus since 9 device addresses are supported. Device address is set via R1 and R2 values on IDx pin. See Figure 22.

The serial control bus consists of two signals and a configuration pin. The SCL is a Serial Bus Clock Input / Output. The SDA is the Serial Bus Data Input / Output signal. Both SCL and SDA signals require an external pull-up resistor to VDD33. For most applications a 4.7 k pull-up resistor to VDD33 may be used. The resistor value may be adjusted for capacitive loading and data rate requirements. The signals are either pulled High, or driven Low.

DS90UB921-Q1 921idx.gif Figure 22. Serial Control Bus Connection

The configuration pin is the IDx pin. This pin sets one of 8 possible device addresses. A pull-up resistor and a pull-down resistor of suggested values may be used to set the voltage ratio of the IDx input (VR2) and VDD33 to select one of the other 8 possible addresses. The voltage range in between the Minimum and Maximum VR2 must be adhered even when taking resistor tolerances into account. The 1% suggested resistors meet this for all cases, but others that also meet the desired voltage range are also acceptable. See Table 6.

Table 6. Serial Control Bus Addresses for IDx

# Minimum Voltage
VR2 (V)(1)
Maximum Voltage VR2
(V)(1)
Suggested Resistor R1 kΩ (1% tol) Suggested Resistor R2 kΩ (1% tol) Address 7'b Address 8'b Appended
1 0.000 0.150 Open 40.2 or Any 0x0C 0x18
2 0.535 0.578 86.6 17.4 0x0E 0x1C
3 0.723 0.775 90.9 26.7 0x10 0x20
4 0.947 0.995 71.5 30.1 0x12 0x24
5 1.203 1.258 84.5 49.9 0x14 0x28
6 1.493 1.565 54.9 47.5 0x16 0x2C
7 1.789 1.855 78.7 97.6 0x18 0x30
8 2.469 2.515 30.9 95.3 0x1A 0x34

The Serial Bus protocol is controlled by START, START-Repeated, and STOP phases. A START occurs when SCL transitions Low while SDA is High. A STOP occurs when SDA transition High while SCL is also HIGH. See Figure 23.

DS90UB921-Q1 30143351.gif Figure 23. Start and Stop Conditions

To communicate with a remote device, the host controller (master) sends the slave address and listens for a response from the slave. This response is referred to as an acknowledge bit (ACK). If a slave on the bus is addressed correctly, it Acknowledges (ACKs) the master by driving the SDA bus low. If the address doesn't match a device's slave address, it Not-acknowledges (NACKs) the master by letting SDA be pulled High. ACKs also occur on the bus when data is being transmitted. When the master is writing data, the slave ACKs after every data byte is successfully received. When the master is reading data, the master ACKs after every data byte is received to let the slave know it wants to receive another data byte. When the master wants to stop reading, it NACKs after the last data byte and creates a stop condition on the bus. All communication on the bus begins with either a Start condition or a Repeated Start condition. All communication on the bus ends with a Stop condition. A READ is shown in Figure 24 and a WRITE is shown in Figure 25.

If the Serial Bus is not required, the three pins may be left open (NC).

DS90UB921-Q1 30143338.gif Figure 24. Serial Control Bus — Read
DS90UB921-Q1 30143339.gif Figure 25. Serial Control Bus — Write

7.6 Register Maps

Table 7. Serial Control Bus Registers

ADD
(dec)
ADD
(hex)
REGISTER NAME BIT(S) TYPE DEFAULT
(hex)
FUNCTION DESCRIPTION
0 0x00 I2C Device ID 7:1 RW Device ID 7–bit address of Serializer
0 RW ID Setting I2C ID Setting
1: Register I2C Device ID (Overrides IDx pin)
0: Device ID is from IDx pin
1 0x01 Reset 7 RW 0x00 Soft Sleep 1: Enable power down when no Bidirectional Control Channel Link detected.
0: Do not power down when no Bidirectional Control Channel Link detected.
6:2 Reserved
1 RW Digital RESET1 Reset the entire digital block including registers
This bit is self-clearing.
1: Reset
0: Normal operation
0 RW Digital RESET0 Reset the entire digital block except registers
This bit is self-clearing
1: Reset
0: Normal operation
3 0x03 Configuration [0] 7 RW 0xD2 Back channel CRC Checker Enable Back Channel Check Enable
1: Enable
0: Disable
6 Reserved
5 RW I2C Remote Write Auto Acknowledge Automatically Acknowledge I2C Remote Write When enabled, I2C writes to the Deserializer (or any remote I2C Slave, if I2C PASS ALL is enabled) are immediately acknowledged without waiting for the Deserializer to acknowledge the write. This allows higher throughput on the I2C bus
1: Enable
0: Disable
4 RW Filter Enable HS, VS, DE two clock filter When enabled, pulses less than two full PCLK cycles on the DE, HS, and VS inputs will be rejected
1: Filtering enable
0: Filtering disable
3 RW I2C Pass-through I2C Pass-Through Mode
1: Pass-Through Enabled
0: Pass-Through Disabled
2 Reserved
1 RW PCLK Auto Switch over to internal OSC in the absence of PCLK
1: Enable auto-switch
0: Disable auto-switch
0 RW TRFB Pixel Clock Edge Select
1: Parallel Interface Data is strobed on the Rising Clock Edge.
0: Parallel Interface Data is strobed on the Falling Clock Edge.
4 0x04 Configuration [1] 7 RW 0x80 Failsafe State Input Failsafe State
1: Failsafe to Low
0: Failsafe to High
6 Reserved
5 RW CRC Error Reset Clear back channel CRC Error Counters
This bit is NOT self-clearing
1: Clear Counters
0: Normal Operation
4 RGB
DE Gate
1: Gate RGB data with DE
0: Pass RGB data independent of DE (default)
This bit is recommended to be set to 1 to avoid unintentionally entering AVMUTE mode. See AVMUTE Operation.
3:2 RW Reserved Reserved
1 RW ALTERNATE FREQUENCY select by pin or register control Frequency range is set by MODE_SEL pin or register, in conjunction with FSEL pin or register 0x35[7:6]. See Frequency Mode Optimizations.
1: Frequency range is set by register. Use register bit reg_0x04[0] to set Alternate Frequency.
0: Frequency range is set by MODE_SEL pin.
0 RW ALTERNATE FREQUENCY Override Value Frequency range select, in conjunction with FSEL pin or register 0x35[7:6].
See Frequency Mode Optimizations.
5 0x05 I2C Control 7:5 0x00 Reserved
4:3 RW SDA Output Delay SDA output delay
Configures output delay on the SDA output. Setting this value will increase output delay in units of 40ns.
Nominal output delay values for SCL to SDA are
00: 240ns
01: 280ns
10: 320ns
11: 360ns
2 RW Local Write Disable Disable remote writes to local registers
Setting the bit to a 1 prevents remote writes to local device registers from across the control channel. It prevents writes to the Serializer registers from an I2C master attached to the Deserializer.
Setting this bit does not affect remote access to I2C slaves at the Serializer
1 RW I2C Bus Timer Speedup Speed up I2C bus watchdog timer
1: Watchdog timer expires after ~50 ms.
0: Watchdog Timer expires after ~1 s
0 RW I2C Bus timer Disable Disable I2C bus watchdog timer
When the I2C watchdog timer may be used to detect when the I2C bus is free or hung up following an invalid termination of a transaction.
If SDA is high and no signalling occurs for ~1 s, the I2C bus assumes to be free. If SDA is low and no signaling occurs, the device attempts to clear the bus by driving 9 clocks on SCL
6 0x06 DES ID 7:1 RW 0x00 DES Device ID 7-bit Deserializer Device ID
Configures the I2C Slave ID of the remote Deserializer. A value of 0 in this field disables I2C access to the remote Deserializer. This field is automatically configured by the Bidirectional Control Channel once RX Lock has been detected. Software may overwrite this value, but should also assert the FREEZE DEVICE ID bit to prevent overwriting by the Bidirectional Control Channel.
0 RW Device ID Frozen Freeze Deserializer Device ID
Prevents autoloading of the Deserializer Device ID by the Bidirectional Control Channel. The ID will be frozen at the value written.
7 0x07 Slave ID 7:1 RW 0x00 Slave Device ID 7-bit Remote Slave Device ID
Configures the physical I2C address of the remote I2C Slave device attached to the remote Deserializer. If an I2C transaction is addressed to the Slave Device Alias ID, the transaction will be remapped to this address before passing the transaction across the Bidirectional Control Channel to the Deserializer
0 Reserved
8 0x08 Slave Alias 7:1 RW 0x00 Slave Device Alias ID 7-bit Remote Slave Device Alias ID
Assigns an Alias ID to an I2C Slave device attached to the remote Deserializer. The transaction will be remapped to the address specified in the Slave ID register. A value of 0 in this field disables access to the remote I2C Slave.
0 Reserved
10 0x0A CRC Errors 7:0 R 0x00 CRC Error LSB Number of back channel CRC errors – 8 least significant bits
11 0x0B 7:0 R 0x00 CRC Error MSB Number of back channel CRC errors – 8 most significant bits
12 0x0C General Status 7:4 0x00 Reserved
3 R BIST CRC Error Back channel CRC error during BIST communication with Deserializer.
The bit is cleared upon loss of link, restart of BIST, or assertion of CRC ERROR RESET in register 0x04.
2 R PCLK Detect PCLK Status
1: Valid PCLK detected
0: Valid PCLK not detected
1 R DES Error Back channel CRC error during communication with Deserializer.
The bit is cleared upon loss of link or assertion of CRC ERROR RESET in register 0x04.
0 R LINK Detect LINK Status
1: Cable link detected
0: Cable link not detected (Fault Condition)
13 0x0D GPIO0 Configuration 7:4 R 0x00 RESERVED Reserved
3 RW GPIO0 Output Value Local GPIO output value
This value is output on the GPIO pin when the GPIO function is enabled, the local GPIO direction is Output, and remote GPIO control is disabled.
2 RW GPIO0 Remote Enable Remote GPIO control
1: Enable GPIO control from remote Deserializer. The GPIO pin will be an output, and the value is received from the remote Deserializer.
0: Disable GPIO control from remote Deserializer.
1 RW GPIO0 Direction Local GPIO Direction
1: Input
0: Output
0 RW GPIO0 Enable GPIO function enable
1: Enable GPIO operation
0: Enable normal operation
14 0x0E GPIO2 and GPIO1 Configurations 7 RW 0x00 GPIO2 Output Value Local GPIO output value
This value is output on the GPIO pin when the GPIO function is enabled, the local GPIO direction is Output, and remote GPIO control is disabled.
6 RW GPIO2 Remote Enable Remote GPIO control
1: Enable GPIO control from remote Deserializer. The GPIO pin will be an output, and the value is received from the remote Deserializer.
0: Disable GPIO control from remote Deserializer.
5 RW GPIO2 Direction Local GPIO Direction
1: Input
0: Output
4 RW GPIO2 Enable GPIO function enable
1: Enable GPIO operation
0: Enable normal operation
3 RW GPIO1 Output Value Local GPIO output value
This value is output on the GPIO pin when the GPIO function is enabled, the local GPIO direction is Output, and remote GPIO control is disabled.
2 RW GPIO1 Remote Enable Remote GPIO control
1: Enable GPIO control from remote Deserializer. The GPIO pin will be an output, and the value is received from the remote Deserializer.
0: Disable GPIO control from remote Deserializer.
1 RW GPIO1 Direction Local GPIO Direction
1: Input
0: Output
0 RW GPIO1 Enable GPIO function enable
1: Enable GPIO operation
0: Enable normal operation
15 0x0F GPO_REG4 and GPIO3 Configurations 7 RW 0x00 GPO_REG4 Output Value Local GPO_REG4 output value
This value is output on the GPO pin when the GPO function is enabled.
(The local GPO direction is Output, and remote GPO control is disabled)
6:5 Reserved
4 RW GPO_REG4 Enable GPO_REG4 function enable
1: Enable GPO operation
0: Enable normal operation
3 RW GPIO3 Output Value Local GPIO output value
This value is output on the GPIO pin when the GPIO function is enabled, the local GPIO direction is Output, and remote GPIO control is disabled.
2 RW GPIO3 Remote Enable Remote GPIO control
1: Enable GPIO control from remote Deserializer. The GPIO pin will be an output, and the value is received from the remote Deserializer.
0: Disable GPIO control from remote Deserializer.
1 RW GPIO3 Direction Local GPIO Direction
1: Input
0: Output
0 RW GPIO3 Enable GPIO function enable
1: Enable GPIO operation
0: Enable normal operation
16 0x10 GPO_REG6 and GPO_REG5 Configurations 7 RW 0x00 GPO_REG6 Output Value Local GPO_REG6 output value
This value is output on the GPO pin when the GPO function is enabled.
(The local GPO direction is Output, and remote GPO control is disabled)
6:5 Reserved
4 RW GPO_REG6 Enable GPO_REG6 function enable
1: Enable GPO operation
0: Enable normal operation
3 RW GPO_REG5 Output Value Local GPO_REG5 output value
This value is output on the GPO pin when the GPO function is enabled, the local GPO direction is Output, and remote GPO control is disabled.
2:1 Reserved
0 RW GPO_REG5 Enable GPO_REG5 function enable
1: Enable GPO operation
0: Enable normal operation
17 0x11 GPO_REG7 Configurations 7:4 RW 0x00 Reserved Reserved
3 RW GPO_REG7 Output Value Local GPO_REG7 output value
This value is output on the GPO pin when the GPO function is enabled, the local GPO direction is Output, and remote GPO control is disabled.
2:1 Reserved
0 RW GPO_REG7 Enable GPO_REG7 function enable
1: Enable GPO operation
0: Enable normal operation
18 0x12 Data Path Control 7:6 0x00 Reserved
5 RW DE Polarity The bit indicates the polarity of the DE (Data Enable) signal.
1: DE is inverted (active low, idle high)
0: DE is positive (active high, idle low)
4 RW I2S Repeater Regen I2S Repeater Regeneration
1: Repeater regenerate I2S from I2S pins
0: Repeater pass through I2S from video pins
3 Reserved
2 RW 18-bit Video Select 18–bit video select
1: Select 18-bit video mode
Note: use of GPIO(s) on unused inputs must be enabled by register.
0: Select 24-bit video mode
1 RW I2S Transport Select I2S Transport Mode Slect
1: Enable I2S Data Forward Channel Frame Transport
0: Enable I2S Data Island Transport
0 Reserved
19 0x13 Mode Status 7:5 0x10 Reserved
4 R MODE_SEL MODE_SEL Status
1: MODE_SEL decode circuit is completed
0: MODE_SEL decode circuit is not completed
3 R Alternate Frequency Mode Alternate Frequency Mode Status
Indicates either Low Frequency mode or Intermediate Frequency mode, depending on FSEL status. See Frequency Mode Optimizations.
2 R Repeater Mode Repeater Mode Status
1: Repeater mode ON
0: Repeater Mode OFF
1 R Reserved
0 R 18-Bit Mode 18-bit Mode Strap Status. The initial strap value can be overridden by register 0x12[2].
1: 18-bit RGB mode
0: 24-bit RGB mode
20 0x14 Oscillator Clock Source and BIST Status 7:3 0x00 Reserved
2:1 RW OSC Clock Source OSC Clock Source
(When LFMODE = 1, Oscillator = 12.5MHz ONLY)
00: External Pixel Clock
01: 33 MHz Oscillator
10: Reserved
11: 25 MHz Oscillator
0 R BIST Enable Status BIST status
1: Enabled
0: Disabled
22 0x16 BCC Watchdog Control 7:1 RW 0xFE Timer Value The watchdog timer allows termination of a control channel transaction if it fails to complete within a programmed amount of time.
This field sets the Bidirectional Control Channel Watchdog Timeout value in units of 2 ms.
This field should not be set to 0
0 RW Timer Control Disable Bidirectional Control Channel Watchdog Timer
1: Disables BCC Watchdog Timer operation
0: Enables BCC Watchdog Timer operation
23 0x17 I2C Control 7 RW 0x5E I2C Pass All I2C Control
1: Enable Forward Control Channel pass-through of all I2C accesses to I2C Slave IDs that do not match the Serializer I2C Slave ID.
0: Enable Forward Control Channel pass-through only of I2C accesses to I2C Slave IDs matching either the remote Deserializer Slave ID or the remote Slave ID.
6 Reserved
5:4 RW SDA Hold Time Internal SDA Hold Time
Configures the amount of internal hold time provided for the SDA input relative to the SCL input. Units are 40 ns
3:0 RW I2C Filter Depth Configures the maximum width of glitch pulses on the SCL and SDA inputs that will be rejected. Units are 5 ns
24 0x18 SCL High Time 7:0 RW 0xA1 SCL HIGH Time I2C Master SCL High Time
This field configures the high pulse width of the SCL output when the Serializer is the Master on the local I2C bus. Units are 40 ns for the nominal oscillator clock frequency. The default value is set to provide a minimum 5us SCL high time with the internal oscillator clock running at 32.5MHz rather than the nominal 25MHz.
25 0x19 SCL Low Time 7:0 RW 0xA5 SCL LOW Time I2C SCL Low Time
This field configures the low pulse width of the SCL output when the Serializer is the Master on the local I2C bus. This value is also used as the SDA setup time by the I2C Slave for providing data prior to releasing SCL during accesses over the Bidirectional Control Channel. Units are 40 ns for the nominal oscillator clock frequency. The default value is set to provide a minimum 5us SCL low time with the internal oscillator clock running at 32.5MHz rather than the nominal 25MHz.
27 0x1B BIST BC Error 7:0 R 0x00 BIST Back Channel CRC Error Counter BIST Mode Back Channel CRC Error Counter
This error counter is active only in the BIST mode. It clears itself at the start of the BIST run.
53 0x35 FSEL Override 7 RW 0 FSEL Register Override Control FSEL Override. FSEL value is set by pin or through register.
0: FSEL set by pin 15 at power-up
1: FSEL is set by register 0x35[6]
6 RW 0 FSEL Override Value This value will be used for FSEL when FSEL Register Override is set (0x35[7]). See Frequency Mode Optimizations.
5:0 RW 0 RESERVED Reserved.
100 0x64 Pattern Generator Control 7:4 RW 0x10 Pattern Generator Select Fixed Pattern Select
This field selects the pattern to output when in Fixed Pattern Mode. Scaled patterns are evenly distributed across the horizontal or vertical active regions. This field is ignored when Auto-Scrolling Mode is enabled. The following table shows the color selections in non-inverted followed by inverted color mode
0000: Reserved
0001: White/Black
0010: Black/White
0011: Red/Cyan
0100: Green/Magenta
0101: Blue/Yellow
0110: Horizontally Scaled Black to White/White to Black
0111: Horizontally Scaled Black to Red/Cyan to White
1000: Horizontally Scaled Black to Green/Magenta to White
1001: Horizontally Scaled Black to Blue/Yellow to White
1010: Vertically Scaled Black to White/White to Black
1011: Vertically Scaled Black to Red/Cyan to White
1100: Vertically Scaled Black to Green/Magenta to White
1101: Vertically Scaled Black to Blue/Yellow to White
1110: Custom color (or its inversion) configured in PGRS, PGGS, PGBS registers
1111: Reserved
3:1 Reserved
0 RW Pattern Generator Enable Pattern Generator Enable
1: Enable Pattern Generator
0: Disable Pattern Generator
101 0x65 Pattern Generator Configuration 7:5 0x00 Reserved
4 RW Pattern Generator 18 Bits 18-bit Mode Select
1: Enable 18-bit color pattern generation. Scaled patterns will have 64 levels of brightness and the R, G, and B outputs use the six most significant color bits.
0: Enable 24-bit pattern generation. Scaled patterns use 256 levels of brightness.
3 RW Pattern Generator External Clock Select External Clock Source
1: Selects the external pixel clock when using internal timing.
0: Selects the internal divided clock when using internal timing
This bit has no effect in external timing mode (PATGEN_TSEL = 0).
2 RW Pattern Generator Timing Select Timing Select Control
1: The Pattern Generator creates its own video timing as configured in the Pattern Generator Total Frame Size, Active Frame Size. Horizontal Sync Width, Vertical Sync Width, Horizontal Back Porch, Vertical Back Porch, and Sync Configuration registers.
0: the Pattern Generator uses external video timing from the pixel clock, Data Enable, Horizontal Sync, and Vertical Sync signals.
1 RW Pattern Generator Color Invert Enable Inverted Color Patterns
1: Invert the color output.
0: Do not invert the color output.
0 RW Pattern Generator Auto-Scroll Enable Auto-Scroll Enable:
1: The Pattern Generator will automatically move to the next enabled pattern after the number of frames specified in the Pattern Generator Frame Time (PGFT) register.
0: The Pattern Generator retains the current pattern.
102 0x66 Pattern Generator Indirect Address 7:0 RW 0x00 Indirect Address This 8-bit field sets the indirect address for accesses to indirectly-mapped registers. It should be written prior to reading or writing the Pattern Generator Indirect Data register.
See AN-2198 (SNLA132).
103 0x67 Pattern Generator Indirect Data 7:0 RW 0x00 Indirect Data When writing to indirect registers, this register contains the data to be written. When reading from indirect registers, this register contains the read back value.
See AN-2198 (SNLA132)
198 0xC6 ICR 7:6 Reserved
5 RW IS_RX_INT Interrupt on Receiver interrupt
Enables interrupt on indication from the Receiver. Allows propagation of interrupts from downstream devices
4:1 Reserved
0 RW INT Enable Global Interrupt Enable
Enables interrupt on the interrupt signal to the controller.
199 0xC7 ISR 7:6 Reserved
5 R IS RX INT Interrupt on Receiver interrupt
Receiver has indicated an interrupt request from down-stream device
4:1 Reserved
0 R INT Global Interrupt
Set if any enabled interrupt is indicated