SNVS891H September   2012  – September 2015 LM3642

PRODUCTION DATA.  

  1. Features
  2. Applications
  3. Description
  4. Revision History
  5. Pin Configuration and Functions
  6. Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
    7. 6.7 Typical Characteristics
  7. Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Power Amplifier Synchronization (TX/TORCH)
      2. 7.3.2 Input Voltage Flash Monitor (IVFM)
      3. 7.3.3 Fault and Protections
        1. 7.3.3.1 Fault Operation
        2. 7.3.3.2 Flash Time-Out
        3. 7.3.3.3 Overvoltage Protection (OVP)
        4. 7.3.3.4 Current Limit
        5. 7.3.3.5 Undervoltage Lockout (UVLO)
        6. 7.3.3.6 Thermal Shutdown (TSD)
        7. 7.3.3.7 LED and/or VOUT Fault
    4. 7.4 Device Functional Modes
      1. 7.4.1 Start-up (Enabling the Device)
      2. 7.4.2 Pass Mode
      3. 7.4.3 Flash Mode
      4. 7.4.4 Torch Mode
      5. 7.4.5 Indicator Mode
    5. 7.5 Programming
      1. 7.5.1 I2C-Compatible Interface
        1. 7.5.1.1 Data Validity
        2. 7.5.1.2 Start and Stop Conditions
        3. 7.5.1.3 Transferring Data
        4. 7.5.1.4 I2C-Compatible Chip Address
        5. 7.5.1.5 Transferring Data
    6. 7.6 Register Map
      1. 7.6.1 Register Descriptions
        1. 7.6.1.1 Enable Register (0x0A)
        2. 7.6.1.2 Flags Register (0x0B)
        3. 7.6.1.3 Flash Features Register (0x08)
        4. 7.6.1.4 Current Control Register (0x09)
        5. 7.6.1.5 Input Voltage Flash Monitor (IVFM) Mode Register (0x01)
        6. 7.6.1.6 Torch Ramp Time Register (0x06)
        7. 7.6.1.7 Silicon Revision Register
  8. Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Output Capacitor Selection
        2. 8.2.2.2 Input Capacitor Selection
        3. 8.2.2.3 Inductor Selection
      3. 8.2.3 Application Curves
  9. Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 Third-Party Products Disclaimer
    2. 11.2 Documentation Support
      1. 11.2.1 Related Documentation
    3. 11.3 Trademarks
    4. 11.4 Community Resources
    5. 11.5 Electrostatic Discharge Caution
    6. 11.6 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

7 Detailed Description

7.1 Overview

The LM3642 is a high-power white LED flash driver capable of delivering up to 1.5 A into a single high-powered LED. The device incorporates a 4-MHz constant frequency-synchronous current-mode PWM boost converter and a single high-side current source to regulate the LED current over the 2.5-V to 5.5-V input voltage range.

The LM3642 PWM converter switches and maintains at least VHR across the current source (LED). This minimum headroom voltage ensures that the current source remains in regulation. If the input voltage is above the LED voltage + current source headroom voltage, the device does not switch and turns the PFET on continuously (Pass Mode). In Pass Mode the difference between (VIN – ILED × RPMOS) and the voltage across the LED is dropped across the current source.

The LM3642 has two logic inputs including a hardware Flash Enable (STROBE) and a Flash Interrupt input (TX/TORCH) designed to interrupt the flash pulse during high battery current conditions. Both logic inputs have internal 300-kΩ (typical) pulldown resistors to GND.

Control of the LM3642 is done via an I2C-compatible interface. This includes adjustment of the Flash and Torch current levels, changing the Flash Timeout Duration and changing the switch current limit. Additionally, there are flag and status bits that indicate flash current time-out, LED failure (open/short), device thermal shutdown, and VIN undervoltage conditions.

7.2 Functional Block Diagram

LM3642 30178905.gif

7.3 Feature Description

7.3.1 Power Amplifier Synchronization (TX/TORCH)

The TX pin is a Power Amplifier Synchronization input. This is designed to reduce the flash LED current and thus limit the battery current during high battery current conditions such as PA transmit events. When the LM3642 is engaged in a Flash event, and the TX pin is pulled high, the LED current is forced into Torch Mode at the programmed Torch current setting. If the TX pin is then pulled low before the Flash pulse terminates, the LED current will return to the previous Flash current level. At the end of the Flash time-out whether the TX pin is high or low, the LED current will turn off.

7.3.2 Input Voltage Flash Monitor (IVFM)

The LM3642 has the ability to adjust the flash current based upon the voltage level present at the IN pin utilizing an Input Voltage Flash Monitor. Upon an IVFM event, the set voltage threshold from the IVFM Mode Register sets the input voltage boundary that forces the LM3642 to stop ramping the flash current during start-up (Stop and Hold Mode).

7.3.3 Fault and Protections

7.3.3.1 Fault Operation

Upon entering a fault condition, the LM3642 will set the appropriate flag in the Flags Register.

7.3.3.2 Flash Time-Out

The Flash Time-Out period sets the amount of time that the Flash Current is being sourced from the current source (LED). The LM3642 has 8 time-out levels ranging 100 ms to 800 ms in 100-ms steps. The Flash Time-Out period is controlled in the Flash Features Register (0x08). Flash Time-Out only applies to the Flash Mode operation. The mode bits in the Enable Register (0x0A) are cleared upon a Flash Time-out.

If an I2C command is used to terminate the flash event, TI recommends selecting a flash time-out level 100 ms above the desired flash duration.

7.3.3.3 Overvoltage Protection (OVP)

The output voltage is limited to typically 5 V (see VOVP in Electrical Characteristics). In situations such as an open LED, the LM3642 will raise the output voltage in order to keep the LED current at its target value. When VOUT reaches 5 V (typ.) the overvoltage comparator will trip and turn off the internal NFET. When VOUT falls below the VOVP Off Threshold, the LM3642 begins switching again. The mode bits in the Enable Register are not cleared upon an OVP.

7.3.3.4 Current Limit

The LM3642 features selectable inductor current limits that are programmable through the Flash Feature Register of the I2C-compatible interface. When the inductor current limit is reached, the LM3642 will terminate the charging phase of the switching cycle.

Since the current limit is sensed in the NMOS switch, there is no mechanism to limit the current when the device operates in Pass Mode. In Boost Mode or Pass Mode if VOUT falls below 2.3 V, the part stops switching, and the PFET operates as a current source limiting the current to 300 mA. This prevents damage to the LM3642 and excessive current draw from the battery during output short-circuit conditions. The mode bits in the Enable Register (0x0A) are not cleared upon a Current Limit event.

NOTE

Pulling additional current from the VOUT node during normal operation is not recommended.

7.3.3.5 Undervoltage Lockout (UVLO)

The LM3642 has an internal comparator that monitors the voltage at IN which will force the LM3642 into shutdown if the input voltage drops to 2.8 V. If the UVLO monitor threshold is tripped, the UVLO flag bit will be set in the Flags Register. If the input voltage rises above 2.8 V, the LM3642 will not be available for operation until there is an I2C read command initiated for the Flags Register. Upon a read, the flag register will be cleared, and normal operation can resume. This feature can be disabled by writing a ‘0’ to the UVLO EN bit in the Input Voltage Flash Monitor Register. The mode bits in the Enable Register are cleared upon a UVLO event.

7.3.3.6 Thermal Shutdown (TSD)

When the LM3642 device’s die temperature reaches 150°C the boost converter shuts down, and the NFET and PFET turn off, as does the current source (LED). When the thermal shutdown threshold is tripped, a '1' gets written to the corresponding bit of the Flags Register (Thermal Shutdown bit), and the LM3642 will go into standby. The LM3642 will only be allowed to restart after the Flags Register is read, clearing the fault flag. Upon restart, if the die temperature is still above 150°C, the LM3642 will reset the fault flag and re-enter standby. The mode bits in the Enable Register are cleared upon a TSD.

7.3.3.7 LED and/or VOUT Fault

The LED Fault flag in the Flags Register reads back a '1' if the part is active in Flash or Torch Mode and the LED output or the VOUT node experiences short condition. The LM3642 determines an LED open condition if the OVP threshold is crossed at the OUT pin while the device is in Flash or Torch Mode. An LED short condition is determined if the voltage at LED goes below 500 mV (typ.) while the device is in Torch or Flash Mode. There is a delay of 256-μs deglitch time before the LED flag is valid and 2.048 ms before the VOUT flag is valid. This delay is the time between when the Flash or Torch current is triggered and when the LED voltage and the output voltage is sampled. The LED flag can be reset by reading back the flags register. The mode bits in the Enable Register are cleared upon an LED and/or VOUT fault.

7.4 Device Functional Modes

7.4.1 Start-up (Enabling the Device)

Turnon of the LM3642 Torch and Flash Modes can be done through the Enable Register. On start-up, when VOUT is less than VIN the internal synchronous PFET turns on as a current source and delivers 350 mA (typ.) to the output capacitor. During this time the current source (LED) is off. When the voltage across the output capacitor reaches 2.2V (typ.), the current source will turn on. At turnon the current source will step through each Flash or Torch level until the target LED current is reached. This gives the device a controlled turnon and limits inrush current from the VIN supply.

7.4.2 Pass Mode

The LM3642 starts up in Pass Mode and stays there until Boost Mode is needed to maintain regulation. If the voltage difference between VOUT and VLED falls below VHR, the device switches to Boost Mode. In Pass Mode the boost converter does not switch and the synchronous PFET turns fully on bringing VOUT up to VIN – ILED × RPMOS. In Pass Mode the inductor current is not limited by the peak current limit. In this situation the output current must be limited to 2 A.

7.4.3 Flash Mode

In Flash Mode, the LED current source (LED) provides 16 target current levels from 93.75 mA to 1500 mA. The Flash currents are adjusted via the Current Control Register. Flash Mode is activated by the Enable Register, or by pulling the STROBE pin HIGH. Once the Flash sequence is activated the current source (LED) will ramp up to the programmed Flash current by stepping through all current steps until the programmed current is reached.

When the part is enabled in the Flash Mode through the Enable Register, all mode bits in the Enable Register are cleared after a flash time-out event.

Table 1 shows the I2C commands and the state of the mode bits, if the STROBE pin is used to enable the Flash Mode.

Table 1. Status of Mode Bits

MODE CHANGE REQUIRED STATUS OF MODE BITS IN THE ENABLE REGISTER AFTER A FLASH
Using Level Triggered STROBE to Flash Mode bits are cleared after a single flash. To reflash, 0x23 will have to be written to 0x0A.

7.4.4 Torch Mode

In Torch Mode, the current source (LED) is programmed via the Current Control Register. Torch Mode is activated by the Enable Register and/or by Enabling the part in TX/Torch pin configuration. Once the Torch Mode is enabled the current source will ramp up to the programmed Torch current level. The Ramp-Up and Ramp-Down times are independently adjustable via the Torch Ramp Register. Torch Mode is not affected by Flash Timeout. In the LM3642, the programmable torch current ranges from 48.4 mA to 375 mA. With the LM3642LT option, the programmable torch current ranges from 24 mA to 187 mA.

7.4.5 Indicator Mode

This mode is activated by the Enable Register. The LM3642 can be programmed to a current level that is 1/8th the torch current value in the Current Control Register. LM3642LT has only one setting of indicator current at 5 mA.

7.5 Programming

7.5.1 I2C-Compatible Interface

7.5.1.1 Data Validity

The data on SDA line must be stable during the HIGH period of the clock signal (SCL). In other words, state of the data line can only be changed when SCL is LOW.

LM3642 30178917.gifFigure 12. Data Validity Diagram

A pullup resistor between the controller's VIO line and SDA must be greater than [(VIO – VOL) / 3 mA] to meet the VOL requirement on SDA. Using a larger pullup resistor results in lower switching current with slower edges, while using a smaller pullup results in higher switching currents with faster edges.

7.5.1.2 Start and Stop Conditions

START and STOP conditions classify the beginning and the end of the I2C session. A START condition is defined as SDA signal transitioning from HIGH to LOW while SCL line is HIGH. A STOP condition is defined as the SDA transitioning from LOW to HIGH while SCL is HIGH. The I2C master always generates START and STOP conditions. The I2C bus is considered to be busy after a START condition and free after a STOP condition. During data transmission, the I2C master can generate repeated START conditions. First START and repeated START conditions are equivalent, function-wise.

LM3642 30178918.gifFigure 13. Start and Stop Conditions

7.5.1.3 Transferring Data

Every byte put on the SDA line must be eight bits long, with the most significant bit (MSB) transferred first. Each byte of data has to be followed by an acknowledge bit. The acknowledge related clock pulse is generated by the master. The master releases the SDA line (HIGH) during the acknowledge clock pulse. The LM3642 pulls down the SDA line during the 9th clock pulse, signifying an acknowledge. The LM3642 generates an acknowledge after each byte is received. There is no acknowledge created after data is read from the LM3642.

After the START condition, the I2C master sends a chip address. This address is seven bits long followed by an eighth bit which is a data direction bit (R/W). The LM3642 7-bit address is 0x63. For the eighth bit, a '0' indicates a WRITE and a '1' indicates a READ. The second byte selects the register to which the data will be written. The third byte contains data to write to the selected register.

LM3642 30178916.gif
w = write (SDA = "0")
r = read (SDA = "1")
ack = acknowledge (SDA pulled down by either master or slave)
id = chip address, 63h for LM3642
Figure 14. Write Cycle

7.5.1.4 I2C-Compatible Chip Address

The device address for the LM3642 is 1100011 (63). After the START condition, the I2C-compatible master sends the 7-bit address followed by an eighth read or write bit (R/W). R/W = 0 indicates a WRITE, and R/W = 1 indicates a READ. The second byte following the device address selects the register address to which the data will be written. The third byte contains the data for the selected register.

LM3642 30178920.gifFigure 15. I2C-Compatible Device Address

7.5.1.5 Transferring Data

Every byte on the SDA line must be eight bits long, with the most significant bit (MSB) transferred first. Each byte of data must be followed by an acknowledge bit (ACK). The acknowledge related clock pulse (9th clock pulse) is generated by the master. The master releases SDA (HIGH) during the 9th clock pulse. The LM3642 pulls down SDA during the 9th clock pulse, signifying an acknowledge. An acknowledge is generated after each byte has been received.

7.6 Register Map

7.6.1 Register Descriptions

Register Name Internal Hex Address Power On/RESET Value
Enable Register 0x0A 00
Flags Register 0x0B 00
Flash Features Register 0x08 52
Current Control Register 0x09 0F
IVFM Mode Register 0x01 80
Torch Ramp Time Register 0x06 00
Silicon Revision Register (LM3642) 0x00 00
Silicon Revision Register (LM3642LT) 0x00 01

7.6.1.1 Enable Register (0x0A)

Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
IVFM
0 = Disabled (default)
1 = Stop and Hold Mode
TX Pin Enable
0 = Disabled (default)
1 = Enabled
Strobe Pin Enable
0 = Disabled (default)
1 = Enabled
Torch Pin Enable
0 = Disabled (default)
1 = Enabled
RFU RFU Mode Bits: M1, M0
00 = Standby (default)
01 = Indicator
10 = Torch
11 = Flash

7.6.1.2 Flags Register (0x0B)

Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
RFU RFU IVFM UVLO Flag OVP Flag LED or VOUT Short Flag Thermal Shutdown Fault Timeout Flag
IVFM IVFM down threshold crossed.
UVLO Fault UVLO Threshold crossed.
OVP Flag Over-voltage Protection tripped. Open Output cap or open LED.
LED Short Fault LED Short detected.
Thermal Shutdown Fault LM3642 die temperature reached thermal shutdown value.
Time-Out Flag Flash Timer tripped.

NOTE

Faults require a read-back of the “Flags Register” to resume operation. Flags report an event occurred, but do not inhibit future functionality. A read-back of the Flags Register will only get updated again if the fault or flags is still present upon a restart.

7.6.1.3 Flash Features Register (0x08)

Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
RFU Inductor Current Limit
0 = 1.6 A
1 = 1.88 A (default)
Flash Ramp Time
000 = 256 µs
001 = 512 µs
010 = 1.024 ms (default)
011 = 2.048 ms
100 = 4.096 ms
101 = 8.192 ms
110 = 16.384 ms
111 = 32.768 ms
Flash Time-Out Time
000 = 100 ms
001 = 200 ms
010 = 300 ms (default)
011 = 400 ms
100 = 500 ms
101 =600 ms
110 = 700 ms
111 = 800 ms

7.6.1.4 Current Control Register (0x09)

Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
RFU Torch Current (LM3642LT)
000 = 48.4 mA (default) (24 mA)
001 =93.74 mA (46.87 mA)
010 =140.63 mA (70.315 mA)
011 = 187.5 mA (93.25 mA)
100 =234.38 mA (117.19 mA)
101 = 281.25 mA (140.625 mA)
110 = 328.13 mA (164.075 mA)
111 = 375 mA (187.5 mA)
Flash Current
0000 = 93.75 mA
0001 = 187.5 mA
0010 = 281.25 mA
0011 = 375 mA
0100 = 468.75 mA
0101 = 562.5 mA
0110 = 656.25 mA
0111 = 750 mA
1000 = 843.75 mA
1001 = 937.5 mA
1010 = 1031.25 mA
1011 = 1125 mA
1100 = 1218.75 mA
1101 = 1312.5 mA
1110 = 1406.25 mA
1111 = 1500 mA (default)

7.6.1.5 Input Voltage Flash Monitor (IVFM) Mode Register (0x01)

Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
UVLO
0 = Disabled
1= Enabled (default)
RFU IVM-D (Down) Threshold
000 = 2.9 V (default)
001 = 3.0 V
010 =3.1 V
011 = 3.2 V
100 = 3.3 V
101 = 3.4 V
110 = 3.5 V
111 = 3.6 V
RFU
    Stop and Hold Mode:Stops Current Ramp and Holds the level for the remaining flash if VIN crosses IVM-D Line. Sets IVFM Flag in Flags Register upon crossing IVM-D Line.
    UVLO EN:If enabled and VIN drops below 2.8 V, the LM3642 will enter standby and set the UVLO flag in the Flags Register. Enabled = ‘1’, Disabled = ‘0’
LM3642 30178903.gifFigure 16. Stop and Hold Mode

7.6.1.6 Torch Ramp Time Register (0x06)

Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1) Bit 0
RFU RFU Torch Ramp-Up Time
000 = 16 ms (default)
001 = 32 ms
010 = 64 ms
011 = 128 ms
100 = 256 ms
101 = 512 ms
110 = 1.024s
111 = 2.048s
Torch Ramp-Down Time
000 = 16 ms (default)
001 = 32 ms
010 = 64 ms
011 = 128 ms
100 = 256 ms
101 = 512 ms
110 = 1.024s
111 = 2.048s

7.6.1.7 Silicon Revision Register

Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
RFU 000 = LM3642