SNVU713 March   2020 LP87525-Q1

 

  1.   LP87525B-Q1 Technical Reference Manual
    1. 1 Introduction
    2. 2 Register Bits Loaded From OTP Memory

1 Introduction

This technical reference manual can be used as a reference for the LP87525B-Q1 default register bits after OTP memory download. This technical reference manual does not provide information about the electrical characteristics, external components, package, or the functionality of the device. For this information and the full register map, refer to the LP8752x-Q1 Four-Phase 10-A Buck Converter With Integrated Switches data sheet.

Table 1 lists the main OTP settings for power rails. Table 2 lists the register bits loaded from OTP memory.

Table 1. Main OTP Settings for Power Rails

Description Bit Name LP87525BRNFRQ1 Value
Device identification OTP configuration OTP_ID 65h
BUCK0, BUCK1 (2-phase operation) Output voltage BUCK0_VSET 850 mV
Enable, EN pin, or I2C register EN_BUCK0, EN_PIN_CTRL0, BUCK0_EN_PIN_SELECT EN1
Force PWM BUCK0_FPWM Yes
Force multiphase BUCK0_FPWM_MP No
Peak current limit N/A 3.5 A
Maximum load current N/A 5 A
Slew rate N/A 1.9 mV/µs
BUCK2, BUCK3 (2-phase operation) Output voltage BUCK2_VSET 855 mV
Enable, EN pin, or I2C register EN_BUCK2, EN_PIN_CTRL2, BUCK2_EN_PIN_SELECT EN1
Force PWM BUCK2_FPWM Yes
Force multiphase BUCK2_FPWM_MP No
Peak current limit N/A 3.5 A
Maximum load current N/A 5 A
Slew rate N/A 1.9 mV/µs
Switching frequency N/A 2 MHz
I2C address N/A 60h

NOTE

The maximum total output capacitance (local + POL) per phase (BUCK0, BUCK1, BUCK2, and BUCK3) depends on the slew rate setting. Check the data sheet for the allowed capacitance value.