SNVU774 April   2021

 

  1.   Trademarks
  2. 1Introduction
    1. 1.1 LM62460RPHEVM Synchronous Step-Down Voltage Converter
  3. 2Quick Start
  4. 3Detailed Descriptions
  5. 4Schematic
  6. 5Board Layout
  7. 6Board Curves
  8. 7Bill of Materials
  9.   Revision History

Board Layout

Figure 5-1 through Figure 5-6 show the board layout for the LM62460RPHEVM. The EVM offers resistors, capacitors, test points, and a jumper to configure the output voltage and precision enable pin, and set frequency and external clock synchronization among the other features of the LM62460-Q1.

The PCB is optimized for thermal performance. The board contains 4 layers. There are 2-oz copper layers on the top and bottom and 1-oz copper mid-layers. The LM62460-Q1 does not have a thermal pad so the best path to move the heat out of the IC is through the pins and into the board. The PGND pins connect to the large GND plane which spreads the heat to the rest of the board. The GND plane also has thermal vias to spread the heat more efficiently to other layers for additional improved thermal performance.

The PCB is also optimized for EMI performance. The layout minimizes the area of high dv/dt nodes like SW and BOOT. The small high-frequency ceramic input capacitors are placed very close to the IC to minimize the loop formed from VIN pins, through the capacitor, to the PGND pins. The board also features an EMI filter on the back-side of the board with options for an inductor, ferrite bead, and filter capacitors to tune the desired EMI performance. The full filter may not be necessary to pass particular EMI requirements but the components and pads are available for flexibility.

The screw terminals J1 and J2 allow for high-current connections to the board. Jumper J3 allows the user to select the output voltage, 5V or 3.3V. Pin voltages can be probed using the test points. The rest of the features can be adjusted by modifying the appropriate resistor values.

Figure 5-1 Top layer and top silkscreen
Figure 5-2 Top layer routing
Figure 5-3 Mid-layer 1 ground plane
Figure 5-4 Mid-layer 2 routing
Figure 5-5 Bottom layer routing
Figure 5-6 Bottom layer and bottom silkscreen