SNVU890 January   2024

 

  1.   1
  2.   Description
  3.   3
  4.   Features
  5.   Applications
  6.   6
  7. 1Evaluation Module Overview
    1. 1.1 Introduction
    2. 1.2 Kit Contents
    3. 1.3 Specification
    4. 1.4 Device Information
    5.     General Texas Instruments High Voltage Evaluation (TI HV EVM) User Safety Guidelines
  8. 2Hardware
    1. 2.1 Test Points
      1. 2.1.1 Key Connections
        1. 2.1.1.1 Connect a Supply to J3 Connector
        2. 2.1.1.2 PWM Input
        3. 2.1.1.3 J1 Connector: Power Supply
    2. 2.2 Power-Up Procedure
      1. 2.2.1 Step 1: Driver Bias Supply
      2. 2.2.2 Step 2: Input Supply
      3. 2.2.3 Step 3: Measure SW Voltage
      4. 2.2.4 Setting Dead-Time
    3. 2.3 Power-Down Procedure
  9. 3Implementation Results
    1. 3.1 Electrical Performance Specifications
      1. 3.1.1 Evaluation Setup
      2. 3.1.2 Performance Data and Results
  10. 4Hardware Design Files
    1. 4.1 Schematic
    2. 4.2 PCB Layouts
    3. 4.3 Bill of Materials
  11. 5Additional Information
    1. 5.1 Trademarks

2.1.1.2 PWM Input

Provide the PWM input using a function generator that is capable of providing the desired switching frequency and duty cycle. This function generator output (0-5V signal) must be connected to the J5 connector as shown in the Figure 3-1. The left-most pin (pin 4) in this view is the positive input of the PWM supply and the remaining three pins are connected to GND in the default assembly for the board. The combination of R14-C22 and R2-C35 generate the dead time for the board. The combination can be adjusted to achieve the best deadtime for the chosen switching frequency.

Alternatively, two separate PWM inputs can be applied to control HI and LI independently. To apply this type of control, R11 must be removed, R13 must be populated with a 0-Ω resistor, and R12 must be replaced with a 10-kΩ resistor. On a board with these modifications, the HI signal must be applied at pin 4 (PWM) of J5, and the LI signal at pin 2 (GND 2) of J5. Note that with this control scheme, the EVM no longer generates a dead time separating HI and LI transitions. Therefore, careful consideration must be applied to the control signals in this mode of operation to prevent a shoot-through condition. When using the low side device to level shift the HI signal to control the high side FET there is an additional propagation delay of 35ns added to the high side signal. This must be considered when programming the deadtime externally. The on-board deadtime generation accounts for this by increasing the turn-on deadtime of the LO signal (R14-C22).

GUID-20240111-SS0I-QWGM-SXZ3-WLX7DQ93F3HB-low.png Figure 2-1 PWM Connection on J5