SNWA014 November   2023 LMH2110

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1Introduction
  5. 2Log Detector System
    1. 2.1 Block Diagram
    2. 2.2 Output Swing Derivation
    3. 2.3 Simulation Results
  6. 3Power Detector – LMH2110
    1. 3.1 Description
    2. 3.2 Log Conformance
    3. 3.3 Calibration
  7. 4Additional Approaches
    1. 4.1 External ADC Approach
    2. 4.2 Single-Ended Approach
  8. 5Summary
  9. 6References

5 Summary

The output of the log detector is used to calculate the VSWR by converting the differential voltage back into power as a fraction, essentially giving the return loss. In the presented example in Section 2.3 the return loss comes out to be 0.056, for which the VSWR is 1.112:1. A VSWR as close to 1 as possible demonstrates excellent matching of the load. Although this app note explains VSWR detection in detail using an external difference amplifier, we can extend this theory to other approaches as well based on the availability and nature of the ADC on the processor/FPGA.