SPAU023A June   2024  – January 2025

 

  1.   1
  2.   Description
  3.   Features
  4.   4
  5. 1Evaluation Module Overview
    1. 1.1 Introduction
    2. 1.2 Kit Contents
    3. 1.3 Specification
      1. 1.3.1 Functional Block Diagram
      2. 1.3.2 Component Identification
  6. 2Hardware
    1. 2.1 System Description
      1. 2.1.1 Key Features
        1. 2.1.1.1 Power Supply
        2. 2.1.1.2 Memory
        3. 2.1.1.3 JTAG Emulator
        4. 2.1.1.4 Supported Interfaces and Peripherals
        5. 2.1.1.5 Expansion Connectors/Headers to Support Application-specific Add‐On Boards
        6. 2.1.1.6 ADC
      2. 2.1.2 Important Usage Notes:
        1. 2.1.2.1 Electrostatic Discharge (ESD) Compliance
        2. 2.1.2.2 IO Cable Length
      3. 2.1.3 Power ON/OFF Procedures
        1. 2.1.3.1 Power-On Procedure
        2. 2.1.3.2 Power-Off Procedure
        3. 2.1.3.3 Power Test Points
      4. 2.1.4 Peripheral and Major Component Description
        1. 2.1.4.1 Clocking
        2. 2.1.4.2 EtherCAT Interface
          1. 2.1.4.2.1 DP83826 PHY Strapping Configuration
        3. 2.1.4.3 Power
          1. 2.1.4.3.1 Power Requirement
          2. 2.1.4.3.2 Power Input
        4. 2.1.4.4 Emulator Connector (TSW-106-16-G-D) and DAC Connector (TSW-102-16-G-D)
          1. 2.1.4.4.1 TSW-106-16-G-D
          2. 2.1.4.4.2 TSW-102-16-G-D
        5. 2.1.4.5 FSI Header
        6. 2.1.4.6 High Density Connector
          1. 2.1.4.6.1 180-pin HSEC Edge Connector
        7. 2.1.4.7 Use Case for HSEC Adapter Board
          1. 2.1.4.7.1 Case 1: Isolated XDS110 on HSEC Adapter, SOM ,Baseboard
          2. 2.1.4.7.2 Case 2: HSEC Adapter, Isolated XDS110 on SOM, Baseboard
  7. 3Hardware Design Files
  8. 4Additional Information
    1. 4.1 Known Hardware or Software Issues
      1. 4.1.1 EVM Usage Notes
    2. 4.2 Trademarks
  9. 5Revision History
2.1.4.2.1 DP83826 PHY Strapping Configuration

The DP83826 PHY uses two-level configurations based on resistor strapping which generate two distinct voltage ranges. The PHY Address strapping is provided for PHY0 to set address -000 and for the PHY1 to set address 001.

Table 2-2 shows the default values of the boot strap configurations.

Table 2-2 EtherCAT PHY Strap Value
Strap Setting Pin Name Strap Function Value of Strap Function Description
PHY address LED0 PHY_ADD0 0/1

PHY0Address:000

PHY1 Address: 001
CRS/LED3 PHY_ADD1 0
COL/LED2 PHY_ADD2 0
MAC Mode selection RX_D2 MAC Mode selection 1 RMII MAC mode
RMII MAC Mode TX_CLK Controller/peripheral mode selection 0 RMII controller mode
RX_D3

RMII_CRS_DV/

RMII_RX_DV

 0 RMII_CRS_DV
Auto negotiation RX_D1 auto MDIX enable/disable 0 auto MDIX enable
RX_D0 auto-negotiation enable/disable 0 auto-negotiation enable
RX_DV MDIX/MDI 0 MDIX
CLKOUT/LED1 RX_ER

CLKOUT 25MHz on Pin 31

LED1 on Pin 31

 1 LED1 on Pin 31
Odd Nibble Detection CLKOUT/LED1 Odd Nibble Detection disabled/enabled 0 Odd Nibble Detection disabled