SPMU411 November   2025 TPS65215-Q1

 

  1.   1
  2.   ABSTRACT
  3.   Trademarks
  4. 1Introduction
  5. 2EEPROM Device Settings
    1. 2.1  Device ID
    2. 2.2  Enable Settings
    3. 2.3  Regulator Voltage Settings
    4. 2.4  Power Sequence Settings
      1. 2.4.1 Power Sequence Settings - Slot assignments
      2. 2.4.2 Power Sequence Settings - Slot Durations
      3. 2.4.3 TPS6521570-Q1 Power Sequence and Example Block Diagram
    5. 2.5  EN / PB / VSENSE Settings
    6. 2.6  Multi-Function Pin Settings
    7. 2.7  Over-Current Deglitch
    8. 2.8  Mask Settings
    9. 2.9  Discharge Check
    10. 2.10 Multi PMIC Config
  6. 3Revision History

2.2 Enable Settings

This section describes the PMIC rails that are enabled in Active and Standby state. Any rail that is disabled by default has the option to be enabled through I2C once the device is in Active state and I2C communication is available.

Table 2-2 Enable Settings - ACTIVE state
PMIC RailRegister NameField NameValueDescription
BUCK1ENABLE_CTRLBUCK1_EN0x1Enabled
BUCK2ENABLE_CTRLBUCK2_EN0x1Enabled
BUCK3ENABLE_CTRLBUCK3_EN0x1Enabled
LDO1ENABLE_CTRLLDO1_EN0x1Enabled
LDO2ENABLE_CTRLLDO2_EN0x1Enabled
GPOGENERAL_CONFIGGPO_EN0x0GPO1 disabled. The output state is low.
GPO2GENERAL_CONFIGGPO2_EN0x0GPO2 disabled. The output state is low.
GPIOGENERAL_CONFIGGPIO_EN0x0GPIO disabled. The output state is low.
Table 2-3 Enable Settings - STANBY (STBY) state
PMIC RailRegister NameField NameValueDescription
BUCK1STBY_1_CONFIGBUCK1_STBY_EN0x1Enabled in STBY Mode
BUCK2STBY_1_CONFIGBUCK2_STBY_EN0x1Enabled in STBY Mode
BUCK3STBY_1_CONFIGBUCK3_STBY_EN0x1Enabled in STBY Mode
LDO1STBY_1_CONFIGLDO1_STBY_EN0x1Enabled in STBY Mode
LDO2STBY_1_CONFIGLDO2_STBY_EN0x1Enabled in STBY Mode
GPO1STBY_2_CONFIGGPO1_STBY_EN0x0Disabled in STBY Mode
GPO2STBY_2_CONFIGGPO2_STBY_EN0x0Disabled in STBY Mode
GPIOSTBY_2_CONFIGGPIO_STBY_EN0x0Disabled in STBY Mode