SPRACI7A October   2018  – March 2022 TMS320F280021 , TMS320F280021-Q1 , TMS320F280023 , TMS320F280023-Q1 , TMS320F280023C , TMS320F280025 , TMS320F280025-Q1 , TMS320F280025C , TMS320F280025C-Q1 , TMS320F280040-Q1 , TMS320F280040C-Q1 , TMS320F280041 , TMS320F280041-Q1 , TMS320F280041C , TMS320F280041C-Q1 , TMS320F280045 , TMS320F280048-Q1 , TMS320F280048C-Q1 , TMS320F280049 , TMS320F280049-Q1 , TMS320F280049C , TMS320F280049C-Q1 , TMS320F28P550SJ , TMS320F28P559SJ-Q1

 

  1.   Trademarks
  2. 1Introduction
    1. 1.1 Overview of Memory Test Requirements
    2. 1.2 Terms and Definitions
  3. 2System Challenges to Memory Validation
    1. 2.1 Memory Test Flow
    2. 2.2 SRAM test Algorithmic Coverage
    3. 2.3 ROM Test Algorithmic Coverage
  4. 3Summary
  5. 4References
  6.   A M-POST Working in F28004x
    1.     A.1 Enabling of Test
    2.     A.2 M-POST Duration
    3.     A.3 M-POST Result
    4.     A.4 Periodic Self-Test
  7.   Revision History

A.4 Periodic Self-Test

The capability described in the document will help support power-on self-test of the memories. If your application needs to support periodic self-test, see C2000™ CPU Memory Built-In Self-Test.