SPRACP6 December   2019 TMS320F2800132 , TMS320F2800133 , TMS320F2800135 , TMS320F2800137 , TMS320F2800152-Q1 , TMS320F2800153-Q1 , TMS320F2800154-Q1 , TMS320F2800155 , TMS320F2800155-Q1 , TMS320F2800156-Q1 , TMS320F2800157 , TMS320F2800157-Q1 , TMS320F280021 , TMS320F280021-Q1 , TMS320F280023 , TMS320F280023-Q1 , TMS320F280023C , TMS320F280025 , TMS320F280025-Q1 , TMS320F280025C , TMS320F280025C-Q1 , TMS320F280040-Q1 , TMS320F280040C-Q1 , TMS320F280041 , TMS320F280041-Q1 , TMS320F280041C , TMS320F280041C-Q1 , TMS320F280045 , TMS320F280048-Q1 , TMS320F280048C-Q1 , TMS320F280049 , TMS320F280049-Q1 , TMS320F280049C , TMS320F280049C-Q1

 

  1.   How to Maximize GPIO Usage in C2000 Devices
    1.     Trademarks
    2. 1 Introduction
    3. 2 Zero Pin Boot Mode Option
      1. 2.1 Weak Pull-Up Method
      2. 2.2 Zero Pin Boot Mode Method
    4. 3 cJTAG Option
    5. 4 Zero Pin Internal Oscillator Option
    6. 5 CMPSS to Save Extra GPIO for Fast Protection
    7. 6 AIO Option
    8. 7 Using the GPDACs as General Purpose Outputs
    9. 8 Optional 1.2-V Internal DCDC
    10. 9 References

Zero Pin Boot Mode Method

Instead of dedicating a set of GPIOs to determine boot mode, the boot mode of the device can be configured as a zero pin option.

With the introduction of the F28004x and newer devices, the number of boot mode select pins can now be customized to support as many as three and as few as zero pins. Using the zero pin option restricts the device to a single boot mode but it frees up the factory default pins to be used for GPIO purposes. Contrary to previous devices which only allowed reconfiguration of the fourth boot mode entry, for the F28004x device, the whole boot mode selection table is customizable. The steps below outline how the device can be configured for zero pin boot to flash:

  1. Customize boot pin configuration:
    1. Set BOOTPIN_CONFIG.BMSP0 to 0xFF
    2. Set BOOTPIN_CONFIG.BMSP1 to 0xFF
    3. Set BOOTPIN_CONFIG.BMSP2 to 0xFF
    4. Set BOOTPIN_CONFIG.KEY to 0x5A for boot ROM to treat these register bits as valid
  2. Flash boot mode configuration.
  3. This is achieved by configuring BOOT_DEF_LOW (0xFFFFFF03) and BOOT_DEF_HIGH (0xFFFFFFFF) user OTP locations as shown in Table 2.

    Table 2. Custom Boot Table

    Boot Mode Number BOOTDEF Name Value
    0 BOOT_DEF0 03(Flash boot)
    1 BOOT_DEF1 0xFF
    2 BOOT_DEF2 0xFF
    3 BOOT_DEF3 0xFF
    4 BOOT_DEF4 0xFF
    5 BOOT_DEF5 0xFF
    6 BOOT_DEF6 0xFF
    7 BOOT_DEF7 0xFF
  4. Writing the values to user OTP.
  5. All the above custom boot configurations take effect by programming the related locations in user-configurable DCSM OTP. The steps below outline one way that can be achieved:

    1. Pick any of the C2000Ware examples project and add the following code snippet above the main function (it can be anywhere in the file just outside the functions):
    2. #pragma RETAIN(otp_z1_data_1) #pragma DATA_SECTION(otp_z1_data_1,"dcsm_zsel_z1_1"); const long otp_z1_data_1 = 0x5AFFFFFF; #pragma RETAIN(otp_z1_data_2) #pragma DATA_SECTION(otp_z1_data_2,"dcsm_zsel_z1_2"); const long otp_z1_data_2 = 0xFFFFFF03;
    3. In the linker command file (e.g 28004x_generic_ram_lnk.cmd), add the following lines:
    4. MEMORY { PAGE 0: DCSM_ZSEL_Z1_P0: origin = 0x07800C, length = 0x000002 DCSM_ZSEL_Z1_P1: origin = 0x07801C, length = 0x000002 } SECTIONS { dcsm_zsel_z1_1 : > DCSM_ZSEL_Z1_P0, PAGE = 0 dcsm_zsel_z1_2 : > DCSM_ZSEL_Z1_P1, PAGE = 0 }
    5. Re-compile the example and load to the target via JTAG using Code Composer Studio™ (CCS). The loader and flash API plugin in CCS will take care of writing these values to OTP location.

For detailed information on the above configurations, see the Device Boot Modes chapter in the TMS320F28004x Piccolo Microcontrollers Technical Reference Manual.

NOTE

OTP locations cannot be re-written, so it is strongly suggested that the Emulation Boot Mode be used to validate the custom modification first. EMU-BOOTPIN-CONFIG and EMU-BOOTDEF can be programmed to experiment with different boot modes without writing to OTP.