SPRACV3 December   2020 AM6412 , AM6422 , AM6442

 

  1.   Trademarks
  2. 1Simulations
    1. 1.1 SerDes
      1. 1.1.1 Introduction
      2. 1.1.2 Simulator Settings and Model Usage
      3. 1.1.3 Simulation Parameters
      4. 1.1.4 Simulation Methodology
      5. 1.1.5 Reviewing Simulation Results
  3. 2Models
    1. 2.1 IBIS-AMI Model Kit
    2. 2.2 The Kit Structure
    3. 2.3 Contents of the Kit
    4. 2.4 IBIS Analog Models
    5. 2.5 Algorithmic Models
      1. 2.5.1 Transmitter (Tx) Model
        1. 2.5.1.1  TX AMI Parameters for Gen 1
        2. 2.5.1.2  TX AMI Parameters for Gen 2
        3. 2.5.1.3  TX AMI Parameters for Gen 3
        4. 2.5.1.4  TX AMI Parameters for Sgmii
        5. 2.5.1.5  TX AMI Parameters for Qsgmii
        6. 2.5.1.6  TX AMI Parameters for USB3.0
        7. 2.5.1.7  TX AMI Parameters for USB3.1
        8. 2.5.1.8  TX AMI Parameters for USXGMII
        9. 2.5.1.9  TX AMI Parameters for Display Port
        10. 2.5.1.10 Transmitter Specifications
        11. 2.5.1.11 TX_Jitter Injection Parameters
      2. 2.5.2 Receiver (Rx) Model
        1. 2.5.2.1 RX AMI Parameters
        2. 2.5.2.2 Rx Jitter Injection Parameters
    6. 2.6 Valid Simulation Condition
    7. 2.7 Eye Mask Requirement

1.1.1 Introduction

The general methodology for evaluating signal integrity for high-speed SERDES interfaces is illustrated in Figure 1-1. This involves running a channel simulation for the serial link. The methodology uses IBIS-Algorithmic Modeling Interface (AMI) models for the Tx/Rx blocks. The basic setup and settings documented here can be used to validate all SerDes links and also across a variety of EDA Signal Integrity simulators. This channel simulation should be performed as a signoff check for all high-speed Serial Link interfaces.

GUID-20201209-CA0I-KJ6T-83SS-9NW8PDPNT42Q-low.png Figure 1-1 Signal Integrity Analysis Setup - Channel Simulation