SPRADD8 November   2024 F29H850TU , F29H859TU-Q1

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1Introduction to Real-Time Control
  5. 2C29 CPU and Key Features
    1. 2.1 Parallel Architecture and Compiler Entitlement
  6. 3C29 Performance Benchmarks
    1. 3.1 Signal Chain Benchmark with ACI Motor Control
    2. 3.2 Real-time Control and DSP Performance
      1. 3.2.1 Examples and Factors Contributing to Results
        1. 3.2.1.1 Saturation (or Limiting) Example
        2. 3.2.1.2 Dead Zone Example
        3. 3.2.1.3 Space Vector Generation (SVGEN) Example
        4. 3.2.1.4 Software Pipelining
      2. 3.2.2 Customer Control and Math Benchmarks
    3. 3.3 General Purpose Processing (GPP) Performance
      1. 3.3.1 Examples and Factors Contributing to Results
        1. 3.3.1.1 Discontinuity Management
        2. 3.3.1.2 Switch() Example
    4. 3.4 Model-Based Design Benchmarks
    5. 3.5 Application Benchmarks
      1. 3.5.1 Single Phase 7kW OBC Description
      2. 3.5.2 Vienna Rectifier-Based Three Phase Power Factor Correction
      3. 3.5.3 Single-Phase Inverter
      4. 3.5.4 Machine Learning
    6. 3.6 Flash Memory Efficiency
    7. 3.7 Code-size Efficiency
  7. 4Summary
  8. 5References

3.2.1.3 Space Vector Generation (SVGEN) Example

Space Vector Generation (SVGEN) is a common function found in motor control systems, where a vector (α, β) is mapped to a 6-segment space vector, to generate 3 PWM signals. In a normal implementation of SVGEN, as shown in Figure 3-5, if..else statements are used (left-side of Figure), and the compiler generates code that contains branches (right-side of Figure).

Normal Implementation of SVGENFigure 3-5 Normal Implementation of SVGEN.

In an optimized implementation of SVGEN, as shown in Figure 3-6, the implementation uses the QUADF instruction of the C29, through an intrinsic, __builtin_c29_quadf32. The instruction breaks up the 2-D space into 16 segments. Then a switch() statement maps the 16-segment space to 6-segment space. The C code is illustrated on the left side of the Figure, and the compiler generated assembly on the right side of the Figure. The generated assembly is now straight line code, without branches, and is parallelized (four instructions in parallel every cycle).

Optimized implementation takes 24 cycles on the C29, irrespective of the inputs, whereas the normal implementation takes 26-43 cycles, depending on the inputs. On the C28, the normal implementation takes 70-100 cycles. On the Cortex-M7, the normal implementation takes 58-73 cycles, depending on the inputs.

Optimized Implementation of SVGEN on C29Figure 3-6 Optimized Implementation of SVGEN on C29.
Attention:

TI provides libraries covering real-time control and DSP. Specific cases where an optimized implementation of a library yields performance improvements over a natural implementation are called out.