SPRZ422K August   2014  – May 2024 TMS320F28374S , TMS320F28375S , TMS320F28375S-Q1 , TMS320F28376S , TMS320F28377S , TMS320F28377S-Q1 , TMS320F28378S , TMS320F28379S

 

  1.   1
  2.   Abstract
  3. 1Usage Notes and Advisories Matrices
    1. 1.1 Usage Notes Matrix
    2. 1.2 Advisories Matrix
  4. 2Nomenclature, Package Symbolization, and Revision Identification
    1. 2.1 Device and Development Support Tool Nomenclature
    2. 2.2 Devices Supported
    3. 2.3 Package Symbolization and Revision Identification
  5. 3Silicon Revision C Usage Notes and Advisories
    1. 3.1 Silicon Revision C Usage Notes
      1. 3.1.1 PIE: Spurious Nested Interrupt After Back-to-Back PIEACK Write and Manual CPU Interrupt Mask Clear
      2. 3.1.2 Caution While Using Nested Interrupts
      3. 3.1.3 SYS/BIOS: Version Implemented in Device ROM is not Maintained
      4. 3.1.4 SDFM: Use Caution While Using SDFM Under Noisy Conditions
      5. 3.1.5 McBSP: XRDY Bit can Hold the Not-Ready Status (0) if New Data is Written to the DX1 Register Without Verifying if the XRDY Bit is in its Ready State (1)
    2. 3.2 Silicon Revision C Advisories
      1.      Advisory
      2.      Advisory
      3.      Advisory
      4.      Advisory
      5.      Advisory
      6.      Advisory
      7.      Advisory
      8.      Advisory
      9.      Advisory
      10.      Advisory
      11.      Advisory
      12.      Advisory
      13.      Advisory
      14.      Advisory
      15.      Advisory
      16.      Advisory
      17.      Advisory
      18.      Advisory
      19.      Advisory
      20.      Advisory
      21.      Advisory
      22.      Advisory
      23.      Advisory
      24.      Advisory
      25.      Advisory
      26.      Advisory
      27.      Advisory
      28.      Advisory
      29.      Advisory
      30.      Advisory
      31.      Advisory
      32.      Advisory
      33.      Advisory
      34.      Advisory
      35.      Advisory
      36.      Advisory
      37.      Advisory
  6. 4Silicon Revision B Usage Notes and Advisories
    1. 4.1 Silicon Revision B Usage Notes
    2. 4.2 Silicon Revision B Advisories
      1.      Advisory
      2.      Advisory
      3.      Advisory
      4.      Advisory
      5.      Advisory
      6.      Advisory
      7.      Advisory
      8.      Advisory
      9.      Advisory
  7. 5Documentation Support
  8. 6Trademarks
  9. 7Revision History

SDFM: Use Caution While Using SDFM Under Noisy Conditions

Revisions Affected: B, C

The SDFM clock input (SDx_Cy) directly clocks the SDFM module when there is no GPIO input synchronization. Any glitches or ringing noise on the SDx_Cy input beyond VIH or VIL can corrupt the SDFM module, leading to unpredictable results.

Workarounds:

SDFM GPIO Asynchronous Mode:

Special attention should be taken during board design to ensure a clean and noise-free signal that meets the SDFM timing requirements. Precautions such as series termination for ringing due to any impedance mismatch of the clock driver, and spacing of traces from other high-frequency signals are recommended.

SDFM GPIO Qualification (3-sample) Mode:

It is highly recommended that the SDFM GPIO qualification mode be used in noisy conditions. This mode provides additional protection by filtering both SDx_Cy and SDx_Dy inputs from system noise. Refer to the "SDFM Timing Requirements When Using GPIO Input Qualification (3-Sample Window)" table in the TMS320F2837xS Real-Time Microcontrollers data sheet when using this option.

When a noise event occurs while using the GPIO Qualification mode, there may still be data disturbance, but it will be proportional to the duration of the noise event and typically filtered by the oversampling of the SDFM module. Below is a relative listing of each SDFM mode's sensitivity to data variation in the presence of severe system noise.

  • Mode 0: This mode is the best performing mode. It is the recommended mode under noisy conditions.
  • Mode 1 and Mode 3: The error in these modes can be twice as large as the error in Mode 0 since each noise glitch can introduce error for multiple data bits.
  • Mode 2: This option is unavailable when using GPIO qualification. This mode is not recommended for either GPIO ASYNC or GPIO qualification.