SSDA008A July   2025  – August 2025 MSPM0C1103 , MSPM0C1104 , MSPM0L1306

 

  1.   1
  2. Description
  3. Required Peripherals
  4. Compatible Devices
  5. Design Steps
  6. Design Considerations
  7. Software Flowchart
  8. Application Code
  9. Results
  10. Additional Resources
  11. 10E2E
  12. 11Trademarks
  13. 12Revision History

Design Considerations

  1. Watchdog window timescale settings: We suggest defining a minimum within 1/32kHz (low sys clock frequency).
  2. Output effective voltage: This code example is determined as low-voltage effective, and the delay time is 10ms. The effective voltage and delay time can be customized, which needs to meet the reset requirement of the monitored device.
  3. The timer counter mode is set with the one-shot down counting. This can be changed in the sysconfig if needed.