SWAU132 April   2024

 

  1.   1
  2.   Description
  3.   Features
  4.   4
  5. 1Evaluation Module Overview
    1. 1.1 Introduction
    2. 1.2 Kit Contents
    3. 1.3 Specification
    4. 1.4 Device Information
  6. 2Hardware
    1. 2.1 Hardware Features
    2. 2.2 Connector and Jumper Descriptions
      1. 2.2.1 LED Indicators
      2. 2.2.2 Jumper Settings
      3. 2.2.3 BoosterPack Header Assignment
      4. 2.2.4 JTAG Headers
    3. 2.3 Power
      1. 2.3.1 Measure the CC3351 Current Draw
        1. 2.3.1.1 Low Current Measurement (LPDS)
        2. 2.3.1.2 Active Current Measurement
    4. 2.4 Clocking
    5. 2.5 Performing Conducted Testing
  7. 3Implementation Results
    1. 3.1 Evaluation Setups
      1. 3.1.1 MCU and RTOS
      2. 3.1.2 Processor and Linux
      3. 3.1.3 Standalone RF Testing
        1. 3.1.3.1 Radio Tool BP-CC3301 Hardware Setup
  8. 4Hardware Design Files
    1. 4.1 Schematics
    2. 4.2 PCB Layouts
    3. 4.3 Bill of Materials (BOM)
  9. 5Additional Information
    1. 5.1 Trademarks

2.2.3 BoosterPack Header Assignment

The CC3351 BoosterPack has 2 x 20 pin connectors that provide access to many of the CC3351 pins and features. The signal assignment on these 2x20 pin connectors is shown in the figure below and described in Table 3-3 and Table 3-4.

GUID-20240405-SS0I-TMLM-KX3F-CCVK7WS8G81N-low.svgFigure 2-3 BP-CC3351 BoosterPack Header Pinout
Table 2-3 P1 Header Pin Assignment
PinName (in schematic)Type/ DirectionDescription
P1.1VCC_MCU_3V3InputNo functional purpose.
P1.2ReservedN/AN/A
P1.3UART_TX_3V3 (from CC3351)OutputThe CC3351 UART TX to host for BLE host controller interface.
P1.4UART_RX_3V3 (to CC3351)InputThe CC3351 UART RX from host for BLE host controller interface.
P1.5LP_RESETInputReset line for CC3351 used to enable/ disable (active low). Driven by host through LaunchPad pins.
P1.6ReservedN/AN/A
P1.7SDIO_CLK_3V3InputSDIO clock or SPI clock. Must be driven by host.
P1.8IRQ_WL_3V3OutputInterrupt request from CC3351 to host for Wi-Fi activity.
P1.9COEX_GRANT_3V3OutputExternal coexistence interface - grant (reserved for future use).
P1.10ANT_SEL_3V3OutputAntenna select control.
P1.21VCC_MCU_5VPower5V supply to board.
P1.22GNDGNDBoard ground
P1.23ReservedN/AN/A
P1.24ReservedN/AN/A
P1.25ReservedN/AN/A
P1.26ReservedN/AN/A
P1.27ReservedN/AN/A
P1.28ReservedN/AN/A
P1.29COEX_REQ_3V3InputExternal coexistence interface - request (reserved for future use).
P1.30COEX_PRIORITY_3V3InputExternal coexistence interface - priority (reserved for future use).
Table 2-4 P2 Header Pin Assignment
PinName (in schematic)Type/DirectionDescription
P2.11IRQ_BLE_3V3OutputInterrupt request from CC3351 to host for BLE activity.
P2.12ReservedN/AN/A
P2.13ReservedN/AN/A
P2.14SDIO_D0_3V3 (POCI)Input/OutputSDIO data D0 or SPI POCI.
P2.15SDIO_CMD_3V3 (PICO)Input/OutputSDIO command or SPI PICO.
P2.16ReservedN/AN/A
P2.17FAST_CLK_REQ_3V3OutputFast clock request from CC3351 to host.
P2.18SDIO_D3_3V3 (CS)Input/OutputSDIO data D3 or SPI CS.
P2.19SLOW_CLK_IN_3V3InputInput for external RTC clock 32.768kHz.
P2.20GNDGNDBoard ground
P2.31ReservedN/AN/A
P2.32ReservedN/AN/A
P2.33ReservedN/AN/A
P2.34LOGGER_3V3OutputTracer from CC3351 (UART TX debug logger).
P2.35ReservedN/AN/A
P2.36UART_RTS_3V3 (from CC3351)OutputUART RTS from CC3351 to host for BLE HCI flow control.
P2.37UART_CTS_3V3 (to CC3351)InputUART CTS to CC3351 from host for BLE HCI flow control.
P2.38SDIO_D1_3V3Input/OutputSDIO data D1.
P2.39SDIO_D2_3V3Input/OutputSDIO data D2.
P2.40ReservedN/AN/A