Figure 1-3 Operation of the ADC

The ADC sequencing process integrates the system interfaces with the SAR ADC modules. The full ADC module supports eight channels, but it uses a Time Division Multiplexing scheme for ADC sample selection. So while the internal ADC operates at 500 Ksps, this round robin behavior across eight channels creates an effective sample rate of 62.5 KHz at each pin. This sampling rate is static for the CC3220 ADC and always collects samples at 62,500 KSPS.

FIFO is used because of the Round Robin behavior of the ADC sampler. ADC Data register changes as it goes through the round robin process, so data is loaded into the FIFO specific to that channel. The FIFO for each channel holds up to 4 words where bits 13:2 hold the ADC sample bits and bits 30:14 has the timestamp for each ADC sample. The FIFO is a buffer, which operates in a first in first out principle. It receives data from from SAR ADC. The FIFO goes into overflow when a write is attempted to a full FIFO, this is due to the software being too slow. The content of the full FIFO is updated with new samples even after FIFO FULL. During FIFO overflow, it is still possible to read data from the FIFO. The FIFO goes into underflow when a read is attempted from an empty FIFO, this is due to software (too many read accesses). After an underflow, it is still possible to write and once the FIFO is no longer empty, it’s possible to read from FIFO.