SWRA779 September   2023 CC3300 , CC3301

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1Introduction
  5. 2Main Features
    1. 2.1 Dual Host Interface
    2. 2.2 Shared Host Interface
    3. 2.3 Autonomous Mode
    4. 2.4 Host Interrupt
      1. 2.4.1 Out-of-Band Interrupt
      2. 2.4.2 In-Band Interrupt
  6. 3Interfaces
    1. 3.1 Introduction
    2. 3.2 SDIO Interface
      1. 3.2.1 SDIO Overview
      2. 3.2.2 SDIO Flow Control
    3. 3.3 SPI Interface
      1. 3.3.1 SPI Overview
      2. 3.3.2 SPI Configuration
      3. 3.3.3 SPI Flow Control
    4. 3.4 Uart Interface
      1. 3.4.1 UART Overview
      2. 3.4.2 UART Configuration
      3. 3.4.3 UART Flow Control
    5. 3.5 Pin Count Options
  7. 4Host Communication
    1. 4.1 Protocol Overview
    2. 4.2 SDIO Wrapper
    3. 4.3 SPI Wrapper
  8. 5Boot Flow
    1. 5.1 SDIO
    2. 5.2 SPI

5 Boot Flow

The host processor may communicate with the companion IC over either SPI or SDIO. The same hardware lines are used for the host interface where the device automatically detect the host interface mode according to a pre-defined sequence. In regards to the host interface, if a dual interface mode is used, the procedure includes a primary host interface (for Wi-Fi) and a secondary host interface (for Bluetooth Low Energy).

Figure 5-1 illustrates the primary interface initialization flow from the host side.

GUID-20230522-SS0I-RG63-ZP2J-GRW7NHQTBGZ3-low.png Figure 5-1 Primary Interface Initialization

After the device is powered on, the host is responsible to send the correct sequence of commands. For SPI mode, a single SDIO command with opcode 0 (CMD0) is sent in order to set the device to SPI mode. For SDIO mode, the sequence includes CMD5/3/7 and then a sequence of CMD52 commands to set additional configuration parameters to the device.

If Bluetooth Low Energy is required, a secondary interface initialization flow may be required. The Bluetooth Low Energy may be used in shared mode or in dual mode (over UART). From the device side, if UART is used then until the UART is properly configured the device shall configure the RTS line as manual controlled GPIO output and assert the RTS to further protect the Core from receiving any host commands until the UART is configured and ready. Figure 5-2 illustrates the secondary interface initialization flow from the device side.

GUID-20230522-SS0I-7TRG-KN4J-CC3T0MJV7RH8-low.png Figure 5-2 Secondary Interface Initialization