SWRZ132B September   2022  – December 2023 CC1354P10

PRODUCTION DATA  

  1.   1
  2.   Trademarks
  3. 1Advisories Matrix
  4. 2Nomenclature, Package Symbolization, and Revision Identification
    1. 2.1 Device and Development Support-Tool Nomenclature
    2. 2.2 Devices Supported
    3. 2.3 Package Symbolization and Revision Identification
  5. 3Advisories
    1.     Radio_01
    2.     Radio_02
    3. 3.1 Radio_05
    4.     Power_03
    5.     PKA_01
    6.     PKA_02
    7.     I2C_01
    8.     I2S_01
    9.     CPU_Sys_01
    10. 3.2 CPU_04
    11.     Sys_01
    12.     SYSCTRL_01
    13.     IOC_01
    14.     ADC_02
    15.     Flash_02
  6. 4Revision History

CPU_Sys_01

The SysTick Calibration Value (Register Field CPU_SCS.STCR.TENMS) Used to Set Up 10 ms Periodic Ticks is Incorrect When the System CPU is Running Off Divided Down 48 MHz Clock

Revisions Affected:

Revision C

Details:

When using the Arm® Cortex® SysTick timer, the TENMS register field (CPU_SCS.STCR.TENMS) will always shows the value corresponding to a 48 MHz CPU clock, regardless of the CPU division factor.

Workarounds:

One of the following two workarounds must be implemented:

Workaround 1: Do not use a divided down system CPU clock. In general, power savings are maximized by completing a task at full clock speed and then stopping the system CPU entirely after the task is complete.

 

Workaround 2: Read the system CPU division factor from the PRCM.CPUCLKDIV.RATIO register and compensate the TENMS field in software based on this value.

TI-provided drivers do not offer any functionality to divide the system CPU clock.