JAJSUE8C August   2008  – April 2024 TL28L92

PRODUCTION DATA  

1.   1
2. 1特長
3. 2概要
4. 3Pin Configurations and Functions
5. 4Electrical Specifications
   1. 4.1 Absolute Maximum Ratings
   2. 4.2 Static Characteristics for 5V Operation
   3. 4.3 Static Characteristics for 3.3V Operation
   4. 4.4 Dynamic Characteristics for 5V Operation
   5. 4.5 Dynamic Characteristics for 3.3V Operation
   6. 4.6 Typical Performance
   7. 4.7 Timing Diagrams
   8. 4.8 Test Information
6. 5Detailed Description
   1. 5.1 Overview
   2. 5.2 Functional Block Diagram
   3. 5.3 Feature Description
      1. 5.3.1 Data Bus Buffer
      2. 5.3.2 Operation Control
      3. 5.3.3 Interrupt Control
      4. 5.3.4 FIFO Configuration
      5. 5.3.5 68xxx Mode
      6. 5.3.6 Timing Circuits
         1. 5.3.6.1  Crystal Clock
         2. 5.3.6.2  Baud Rate Generator
         3. 5.3.6.3  Counter/Timer
         4. 5.3.6.4  Timer Mode
         5. 5.3.6.5  Counter Mode
         6. 5.3.6.6  Time-Out Mode
         7. 5.3.6.7  Time-Out Mode Caution
         8. 5.3.6.8  Communications Channels A and B
         9. 5.3.6.9  Input Port
         10. 5.3.6.10 Output Port
      7. 5.3.7 Operation
         1. 5.3.7.1 Transmitter
         2. 5.3.7.2 Receiver
         3. 5.3.7.3 Transmitter Reset and Disable
         4. 5.3.7.4 Receiver FIFO
         5. 5.3.7.5 Receiver Status Bits
         6. 5.3.7.6 Receiver Reset and Disable
         7. 5.3.7.7 Watchdog
         8. 5.3.7.8 Receiver Time-Out Mode
         9. 5.3.7.9 Time-Out Mode Caution
7. 6Programming
   1. 6.1 Register Overview
   2. 6.2 Condensed Register Bit Formats
   3. 6.3 Register Descriptions
      1. 6.3.1  Mode Registers
         1. 6.3.1.1 Mode Register 0 Channel A (MR0A)
         2. 6.3.1.2 Mode Register 1 Channel A (MR1A)
         3. 6.3.1.3 Mode Register 2 Channel A (MR2A)
         4. 6.3.1.4 Mode Register 0 Channel B (MR0B)
         5. 6.3.1.5 Mode Register 1 Channel B (MR1B)
         6. 6.3.1.6 Mode Register 2 Channel B (MR2B)
      2. 6.3.2  Clock Select Registers
         1. 6.3.2.1 Clock Select Register Channel A (CSRA)
         2. 6.3.2.2 Clock Select Register Channel B (CSRB)
      3. 6.3.3  Command Registers
         1. 6.3.3.1 Command Register Channel A (CRA)
         2. 6.3.3.2 Command Register Channel B (CRB)
      4. 6.3.4  Status Registers
         1. 6.3.4.1 Status Register Channel A (SRA)
         2. 6.3.4.2 Status Register Channel B (SRB)
      5. 6.3.5  Output Configuration Control Register (OPCR)
      6. 6.3.6  Set Output Port Bits Register (SOPR)
      7. 6.3.7  Reset Output Port Bits Register (ROPR)
      8. 6.3.8  Output Port Register (OPR)
      9. 6.3.9  Auxiliary Control Register (ACR)
      10. 6.3.10 Input Port Change Register (IPCR)
      11. 6.3.11 Interrupt Status Register (ISR)
      12. 6.3.12 Interrupt Mask Register (IMR)
      13. 6.3.13 Interrupt Vector Register (IVR; 68xxx Mode) or General Purpose Register (GP; 80xxx Mode)
      14. 6.3.14 Counter and Timer Registers
   4. 6.4 Output Port Notes
   5. 6.5 CTS, RTS, CTS Enable Tx Signals
8. 7Device and Documentation Support
   1. 7.1 ドキュメントの更新通知を受け取る方法
   2. 7.2 サポート・リソース
   3. 7.3 Trademarks
   4. 7.4 静電気放電に関する注意事項
   5. 7.5 用語集
9. 8Revision History
10. 9Mechanical, Packaging, and Orderable Information

TL28L92 3.3V～5V デュアル、ユニバーサル非同期レシーバ / トランスミッタ

このリソースの元の言語は英語です。 翻訳は概要を便宜的に提供するもので、自動化ツール (機械翻訳) を使用していることがあり、TI では翻訳の正確性および妥当性につきましては一切保証いたしません。 実際の設計などの前には、ti.com で必ず最新の英語版をご参照くださいますようお願いいたします。

最新の英語版をダウンロード