DLPS112D June   2018  – March 2026 DLPC3479

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1  Absolute Maximum Ratings
    2. 5.2  ESD Ratings
    3. 5.3  Recommended Operating Conditions
    4. 5.4  Thermal Information
    5. 5.5  Power Electrical Characteristics
    6. 5.6  Pin Electrical Characteristics
    7. 5.7  Internal Pullup and Pulldown Electrical Characteristics
    8. 5.8  DMD SubLVDS Interface Electrical Characteristics
    9. 5.9  DMD Low-Speed Interface Electrical Characteristics
    10. 5.10 System Oscillator Timing Requirements
    11. 5.11 Power Supply and Reset Timing Requirements
    12. 5.12 Parallel Interface Frame Timing Requirements
    13. 5.13 Parallel Interface General Timing Requirements
    14. 5.14 Flash Interface Timing Requirements
    15. 5.15 Other Timing Requirements
    16. 5.16 DMD SubLVDS Interface Switching Characteristics
    17. 5.17 DMD Parking Switching Characteristics
    18. 5.18 Chipset Component Usage Specification
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1  Input Source Requirements
        1. 6.3.1.1 Supported Resolution and Frame Rates
        2. 6.3.1.2 3D Display
        3. 6.3.1.3 Parallel Interface
          1. 6.3.1.3.1 PDATA Bus—Parallel Interface Bit Mapping Modes
      2. 6.3.2  Pattern Display
        1. 6.3.2.1 External Pattern Mode
          1. 6.3.2.1.1 8-Bit Monochrome Patterns
          2. 6.3.2.1.2 1-Bit Monochrome Patterns
        2. 6.3.2.2 Internal Pattern Mode
          1. 6.3.2.2.1 Free Running Mode
          2. 6.3.2.2.2 Trigger In Mode
      3. 6.3.3  Device Start-Up
      4. 6.3.4  SPI Flash
        1. 6.3.4.1 SPI Flash Interface
        2. 6.3.4.2 SPI Flash Programming
      5. 6.3.5  I2C Interface
      6. 6.3.6  Content Adaptive Illumination Control (CAIC)
      7. 6.3.7  Local Area Brightness Boost (LABB)
      8. 6.3.8  3D Glasses Operation
      9. 6.3.9  Test Point Support
      10. 6.3.10 DMD Interface
        1. 6.3.10.1 SubLVDS (HS) Interface
    4. 6.4 Device Functional Modes
    5. 6.5 Programming
  8. 7 Application and Implementation
    1. 7.1 Application Information
    2. 7.2 Typical Application
      1. 7.2.1 Design Requirements
      2. 7.2.2 Detailed Design Procedure
      3. 7.2.3 Application Curve
  9. 8 Power Supply Recommendations
    1. 8.1 PLL Design Considerations
    2. 8.2 System Power-Up and Power-Down Sequence
    3. 8.3 Power-Up Initialization Sequence
    4. 8.4 DMD Fast Park Control (PARKZ)
    5. 8.5 Hot Plug I/O Usage
  10. 9 Layout
    1. 9.1 Layout Guidelines
      1. 9.1.1 PLL Power Layout
      2. 9.1.2 Reference Clock Layout
        1. 9.1.2.1 Recommended Crystal Oscillator Configuration
      3. 9.1.3 Unused Pins
      4. 9.1.4 DMD Control and SubLVDS Signals
      5. 9.1.5 Layer Changes
      6. 9.1.6 Stubs
      7. 9.1.7 Terminations
      8. 9.1.8 Routing Vias
      9. 9.1.9 Thermal Considerations
    2. 9.2 Layout Example
  11. 10Device and Documentation Support
    1. 10.1 Device Support
      1. 10.1.1 Third-Party Products Disclaimer
      2. 10.1.2 Device Nomenclature
        1. 10.1.2.1 Device Markings
      3. 10.1.3 Video Timing Parameter Definitions
    2. 10.2 Documentation Support
    3. 10.3 Receiving Notification of Documentation Updates
    4. 10.4 Support Resources
    5. 10.5 Trademarks
    6. 10.6 Electrostatic Discharge Caution
    7. 10.7 Glossary
  12. 11Revision History
  13. 12Mechanical, Packaging, and Orderable Information

4 Pin Configuration and Functions

DLPC3479 ZEZ Package201-Pin NFBGABottom ViewFigure 4-1 ZEZ Package201-Pin NFBGABottom View
DLPC3479 13-mm × 13-mm Package – VF Ball Grid ArrayFigure 4-2 13-mm × 13-mm Package – VF Ball Grid Array
Table 4-1 Test Pins and General Control
PINI/OTYPE(4)DESCRIPTION
NAMENO.
HWTEST_ENC10I6Manufacturing test enable signal. Connect this signal directly to ground on the PCB for normal operation.
PARKZC13I6DMD fast park control (active low Input with a hysteresis buffer). This signal is used to quickly park the DMD when loss of power is imminent. The longest lifetime of the DMD may not be achieved with the fast park operation, therefore, this signal is intended to only be asserted when a normal park operation is unable to be completed. The PARKZ signal is typically provided from the DLPAxxxx interrupt output signal.
JTAGTCKP12I6TI internal use. Leave this pin unconnected.
JTAGTDIP13I6TI internal use. Leave this pin unconnected.
JTAGTDO1N13(1)O1TI internal use. Leave this pin unconnected.
JTAGTDO2N12(1)O1TI internal use. Leave this pin unconnected.
JTAGTMS1M13I6TI internal use. Leave this pin unconnected.
JTAGTMS2N11I6TI internal use. Leave this pin unconnected.
JTAGTRSTZP11I6TI internal use.
This pin must be tied to ground, through an external resistor for normal operation. Failure to tie this pin low during normal operation can cause start up and initialization problems.(2)
RESETZC11I6Power-on reset (active low input with a hysteresis buffer). Self-configuration starts when a low-to-high transition is detected on RESETZ. All controller power and clocks must be stable before this reset is deasserted. No signals are in their active state while RESETZ is asserted. This pin is typically connected to the RESETZ pin of the DLPA200x or RESET_Z of the DLPA300X.
TSTPT_0R12I/O1Test pins (includes weak internal pulldown). Pins are tristated while RESETZ is asserted low. Sampled as an input test mode selection control approximately 1.5µs after deassertion of RESETZ, and then driven as outputs.(2)(3)

Normal use: reserved for test output. Leave open for normal use.
Note: An external pullup may put the DLPC34xx in a test mode. See Section 6.3.9 for more information.
TSTPT_1R13I/O1
TSTPT_2R14I/O1
TSTPT_3R15I/O1
TSTPT_4P14I/O1Test pin 4 (includes weak internal pulldown) – tristated while RESETZ is asserted low. Sampled as an input test mode selection control approximately 1.5µs after deassertion of RESETZ and then driven as an output. Reserved for TRIG_OUT_1 signal (output).
TSTPT_5P15I/O1Test pins (includes weak internal pulldown). Pins are tristated while RESETZ is asserted low. Sampled as an input test mode selection control approximately 1.5µs after deassertion of RESETZ, and then driven as outputs.(2)(3)

Normal use: reserved for test output. Leave open for normal use.
Note: An external pullup may put the DLPC34xx in a test mode. See Section 6.3.9 for more information.
TSTPT_6N14I/O1
TSTPT_7N15I/O1
(1) If the application design does not require an external pullup, and there is no external logic that can overcome the weak internal pulldown resistor, then this I/O pin can be left open or unconnected for normal operation. If the application design does not require an external pullup, but there is external logic that might overcome the weak internal pulldown resistor, then an external pulldown is recommended to ensure a logic low.
(2) The external resistor must have a value of 8kΩ or less to compensate for pins that provide the internal pullup or pulldown resistors.
(3) If the application design does not require an external pullup and there is no external logic that can overcome the weak internal pulldown, then the TSTPT I/O can be left open (unconnected) for normal operation. If the operation does not call for an external pullup, but there is external logic that might overcome the weak internal pulldown resistor, then an external pulldown resistor is recommended to ensure a logic low.
(4) See Table 4-9 for type definitions.
Table 4-2 Parallel Port Input
PIN(1)(2)I/OTYPE(4)DESCRIPTION
NAMENO.PARALLEL RGB MODE
PCLKP3I10Pixel clock
PDM_CVS_TEN4I/O5Parallel data mask. Programable polarity with default of active high. Optional signal.
VSYNC_WEP1I10Vsync(3)
HSYNC_CSN5I10Hsync(3)
DATAEN_CMDP2I10Data valid
(TYPICAL RGB 888)
PDATA_0
PDATA_1
PDATA_2
PDATA_3
PDATA_4
PDATA_5
PDATA_6
PDATA_7		K2
K1
L2
L1
M2
M1
N2
N1		I10Blue (bit weight 1)
Blue (bit weight 2)
Blue (bit weight 4)
Blue (bit weight 8)
Blue (bit weight 16)
Blue (bit weight 32)
Blue (bit weight 64)
Blue (bit weight 128)
(TYPICAL RGB 888)
PDATA_8
PDATA_9
PDATA_10
PDATA_11
PDATA_12
PDATA_13
PDATA_14
PDATA_15		R1
R2
R3
P4
R4
P5
R5
P6		I10Green (bit weight 1)
Green (bit weight 2)
Green (bit weight 4)
Green (bit weight 8)
Green (bit weight 16)
Green (bit weight 32)
Green (bit weight 64)
Green (bit weight 128)
(TYPICAL RGB 888)
PDATA_16
PDATA_17
PDATA_18
PDATA_19
PDATA_20
PDATA_21
PDATA_22
PDATA_23		R6
P7
R7
P8
R8
P9
R9
P10		I10Red (bit weight 1)
Red (bit weight 2)
Red (bit weight 4)
Red (bit weight 8)
Red (bit weight 16)
Red (bit weight 32)
Red (bit weight 64)
Red (bit weight 128)
3DRN6I10Light Control
  • External input trigger signal for Internal Pattern mode (input)
3D reference
  • For 3D applications: left or right 3D reference (left = 1, right = 0). To be provided by the host. Must transition in the middle of each frame (no closer than 1 ms to the active edge of VSYNC)
  • If a 3D application is not used, pull this input low through an external resistor.
(1) PDATA(23:0) bus mapping depends on pixel format and source mode. See later sections for details.
(2) Connect unused inputs to ground or pulldown to ground through an external resistor (8kΩ or less).
(3) VSYNC and HSYNC polarity can be adjusted by software.
(4) See Table 4-9 for type definitions.
Table 4-3 DMD Reset and Bias Control
PINI/OTYPE(1)DESCRIPTION
NAMENO.
DMD_DEN_ARSTZB1O2DMD driver enable (active high). DMD reset (active low). When corresponding I/O power is supplied, the controller drives this signal low after the DMD is parked and before power is removed from the DMD. If the 1.8V power to the DLPC34xx is independent of the 1.8V power to the DMD, then TI recommends including a weak, external pulldown resistor to hold the signal low in case DLPC34xx power is inactive while DMD power is applied.
DMD_LS_CLKA1O3DMD, low speed (LS) interface clock
DMD_LS_WDATAA2O3DMD, low speed (LS) serial write data
DMD_LS_RDATAB2I6DMD, low speed (LS) serial read data
(1) See Table 4-9 for type definitions.
Table 4-4 DMD SubLVDS Interface
PINI/OTYPE(1)DESCRIPTION
NAMENO.
DMD_HS_CLK_P
DMD_HS_CLK_N		A7
B7		O4DMD high speed (HS) interface clock
DMD_HS_WDATA_H_P
DMD_HS_WDATA_H_N
DMD_HS_WDATA_G_P
DMD_HS_WDATA_G_N
DMD_HS_WDATA_F_P
DMD_HS_WDATA_F_N
DMD_HS_WDATA_E_P
DMD_HS_WDATA_E_N
DMD_HS_WDATA_D_P
DMD_HS_WDATA_D_N
DMD_HS_WDATA_C_P
DMD_HS_WDATA_C_N
DMD_HS_WDATA_B_P
DMD_HS_WDATA_B_N
DMD_HS_WDATA_A_P
DMD_HS_WDATA_A_N		A3
B3
A4
B4
A5
B5
A6
B6
A8
B8
A9
B9
A10
B10
A11
B11		O4DMD SubLVDS high speed (HS) interface write data lanes. The true numbering and application of the DMD_HS_WDATA pins depend on the software configuration. See Table 6-10.
(1) See Table 4-9 for type definitions.
Table 4-5 Peripheral Interface
PINI/OTYPE(3)DESCRIPTION(1)
NAMENO.
CMP_OUTA12I6Successive approximation ADC (analog-to-digital converter) comparator output (DLPC34xx Input). To implement, use a successive approximation ADC with a thermistor feeding one input of the external comparator and the DLPC34xx controller GPIO_10 (RC_CHARGE) pin driving the other side of the comparator. It is recommended to use the DLPAxxxx to achieve this function. CMP_OUT must be pulled-down to ground if this function is not used (hysteresis buffer).
CMP_PWMA15O1TI internal use. Leave this pin unconnected.
HOST_IRQ(2)N8O9Host interrupt (output)
HOST_IRQ indicates when the DLPC34xx auto-initialization is in progress and, most importantly when it completes.
This pin is tristated during reset. An external pullup must be included on this signal.
IIC0_SCL(4)N10I/O7I2C target (port 0) SCL (bidirectional, open-drain signal with input hysteresis): This pin requires an external pullup resistor. The target I2C I/Os are 3.6V tolerant (high-voltage-input tolerant) and are powered by VCC_INTF (which can be 1.8, 2.5, or 3.3V). External I2C pullups must be connected to a host supply with an equal or higher supply voltage, up to a maximum of 3.6V (a lower pullup supply voltage does not typically satisfy the VIH specification of the target I2C input buffers).
IIC1_SCLR11I/O8TI internal use. TI recommends an external pullup resistor.
IIC0_SDA(4)N9I/O7I2C target (port 0) SDA. (bidirectional, open-drain signal with input hysteresis): This pin requires an external pullup resistor. The target I2C port is the control port of the controller. The target I2C I/O pins are 3.6V tolerant (high-volt-input tolerant) and are powered by VCC_INTF (which can be 1.8, 2.5, or 3.3V). External I2C pullups must be connected to a host supply with an equal or higher supply voltage, up to a maximum of 3.6V (a lower pullup supply voltage does not typically satisfy the VIH specification of the target I2C input buffers).
IIC1_SDAR10I/O8TI internal use. TI recommends an external pullup resistor.
LED_SEL_0B15O1LED enable select. Automatically controlled by the DLPC34xx programmable DMD sequence
LED_SEL(1:0)
00
01
10
11		Enabled LED
None
Red
Green
Blue
LED_SEL_1B14O1The controller drives these signals low when RESETZ is asserted and the corresponding I/O power is supplied. The controller continues to drive these signals low throughout the auto-initialization process. A weak, external pulldown resistor is recommended to ensure that the LEDs are disabled when I/O power is not applied.
SPI0_CLKA13O13SPI (Serial Peripheral Interface) port 0, clock. This pin is typically connected to the flash memory clock.
SPI0_CSZ0A14O13SPI port 0, chip select 0 (active low output). This pin is typically connected to the flash memory chip select.
TI recommends an external pullup resistor to avoid floating inputs to the external SPI device during controller reset assertion.
SPI0_CSZ1C12O13SPI port 0, chip select 1 (active low output). This pin typically remains unused.
TI recommends an external pullup resistor to avoid floating inputs to the external SPI device during controller reset assertion.
SPI0_DINB12I12Synchronous serial port 0, receive data in. This pin is typically connected to the flash memory data out.
SPI0_DOUTB13O13Synchronous serial port 0, transmit data out. This pin is typically connected to the flash memory data in.
(1) External pullup resistor must be 8kΩ or less.
(2) For more information about usage, see Section 6.3.3.
(3) See Table 4-9 for type definitions.
(4) When VCC_INTF is powered and VDD is not powered, the controller may drive the IIC0_xxx pins low, which prevents communication on this I2C bus. Do not power up the VCC_INTF pin before powering up the VDD pin for any system that has additional target devices on this bus.
Table 4-6 GPIO Peripheral Interface
PINI/OTYPE(3)DESCRIPTION(2)
NAME(1)NO.
GPIO_19M15I/O1HBT_ODAT (Output): Connect to the HBT_IDAT (GPIO_17) pin of the second DLPC3479.
GPIO_18M14I/O1HBT_OCLK (Output): Connect to the HBT_ICLK (GPIO_16) pin of the second DLPC3479.
GPIO_17L15I/O1HBT_IDAT (Input): Connect to the HBT_ODAT (GPIO_19) pin of the second DLPC3479.
GPIO_16L14I/O1HBT_ICLK (Input): Connect to the HBT_OCLK (GPIO_18) pin of the second DLPC3479.
GPIO_15K15I/O1DA_SYNC (BiDir): Connect to the DA_SYNC (GPIO_15) pin of the second DLPC3479.
GPIO_14K14I/O1SEQ_SYNC (BiDir): Connect to the SEQ_SYNC (GPIO_14) pin of the second DLPC3479 with a 7.87k pullup resistor to VCC18.
GPIO_13J15I/O1General-purpose I/O 13 (hysteresis buffer). Optional GPIO. If unused TI recommends this pin be configured as a logic zero GPIO output and left unconnected. Otherwise this pin requires an external pullup or pulldown to avoid a floating GPIO input.
GPIO_12J14I/O1General-purpose I/O 12 (hysteresis buffer). Optional GPIO. If unused TI recommends this pin be configured as a logic zero GPIO output and left unconnected. Otherwise this pin requires an external pullup or pulldown to avoid a floating GPIO input.
GPIO_11H15I/O1General-purpose I/O 11 (hysteresis buffer). Options:
  1. Thermistor power enable (output). Turns on the power to the thermistor when it is used and enabled.
  2. Optional GPIO. If unused TI recommends this pin be configured as a logic zero GPIO output and left unconnected. Otherwise this pin requires an external pullup or pulldown to avoid a floating GPIO input.
GPIO_10H14I/O1General-purpose I/O 10 (hysteresis buffer). Options:
  1. RC_CHARGE (output): Intended to feed the RC charge circuit of the thermistor interface.
  2. Optional GPIO. If unused TI recommends this pin be configured as a logic zero GPIO output and left unconnected. Other,wise this pin requires an external pullup or pulldown to avoid a floating GPIO input.
GPIO_09G15I/O1General-purpose I/O 09 (hysteresis buffer). Optional GPIO. If unused TI recommends this pin be configured as a logic zero GPIO output and left unconnected. Otherwise this pin requires an external pullup or pulldown to avoid a floating GPIO input.
GPIO_08G14I/O1General-purpose I/O 08 (hysteresis buffer). Normal mirror parking request (active low): To be driven by the PROJ_ON output of the host. A logic low on this signal causes the DLPC34xx to PARK the DMD, but it does not power down the DMD (the DLPAxxxx does that instead). The minimum high time is 200ms. The minimum low time is 200ms.
GPIO_07F15I/O1General-purpose I/O 07 (hysteresis buffer). Options:
  1. Light Control: Reserved for TRIG_OUT_2 signal (output).
  2. Optional GPIO. Should be configured as a logic zero GPIO output and left unconnected if not used (otherwise it will require an external pullup or pulldown to avoid a floating GPIO input).
GPIO_06F14I/O1General-purpose I/O 06 (hysteresis buffer). Option:
  1. Light Control: Reserved for pattern ready signal (Output). Applicable in Internal Pattern Streaming Mode only.
  2. Optional GPIO. Should be configured as a logic zero GPIO output and left unconnected if not used (otherwise it will require an external pullup or pulldown to avoid a floating GPIO input).
GPIO_05E15I/O1General-purpose I/O 05 (hysteresis buffer). Optional GPIO. If unused TI recommends this pin be configured as a logic zero GPIO output and left unconnected. Otherwise this pin requires an external pullup or pulldown to avoid a floating GPIO input.
GPIO_04E14I/O1MST_SLVZ (Input): Primary or secondary controller identifier signal (Primary = 1, secondary = 0).
GPIO_03D15I/O1General-purpose I/O 03 (hysteresis buffer). SPI1_CSZ0 (active low output): SPI1 chip select 0 signal. This pin is typically connected to the DLPAxxxx SPI_CSZ pin. Requires an external pullup resistor to deactivate this signal during reset and auto-initialization processes.
GPIO_02D14I/O1General-purpose I/O 02 (hysteresis buffer). SPI1_DOUT (output): SPI1 data output signal. This pin is typically connected to the DLPAxxxx SPI_DIN pin.
GPIO_01C15I/O1General-purpose I/O 01 (hysteresis buffer). SPI1_CLK (output): SPI1 clock signal. This pin is typically connected to the DLPAxxxx SPI_CLK pin.
GPIO_00C14I/O1General-purpose I/O 00 (hysteresis buffer). SPI1_DIN (input): SPI1 data input signal. This pin is typically connected to the DLPAxxxx SPI_DOUT pin.
(1) GPIO pins must be configured through software for input, output, bidirectional, or open-drain operation. Some GPIO pins have one or more alternative use modes, which are also software configurable. An external pullup resistor is required for each signal configured as open-drain.
(2) General-purpose I/O for the DLPC3470 controller. These GPIO pins are software configurable.
(3) See Table 4-9 for type definitions.
Table 4-7 Clock and PLL Support
PINI/OTYPE(1)DESCRIPTION
NAMENO.
PLL_REFCLK_IH1I11Reference clock crystal input. If an external oscillator is used instead of a crystal, use this pin as the oscillator input.
PLL_REFCLK_OJ1O5Reference clock crystal return. If an external oscillator is used instead of a crystal, leave this pin unconnected (floating with no added capacitive load).
(1) See Table 4-9 for type definitions.
Table 4-8 Power and Ground
PINI/OTYPEDESCRIPTION
NAMENO.
VDDC5, D5, D7, D12, J4, J12, K3, L4, L12, M6, M9, D9, D13, F13, H13, L13, M10, D3, E3—PWRCore 1.1V power (main 1.1V)
VDDLP12C3—---Unused. It is recommended to externally tie this pin to VDD.
VSSC4, D6, D8, D10, E4, E13, F4, G4, G12, H4, H12, J3, J13, K4, K12, L3, M4, M5, M8, M12 G13, C6, C8, F6, F7, F8, F9, F10, G6, G7, G8, G9, G10, H6, H7, H8, H9, H10, J6, J7, J8, J9, J10, K6, K7, K8, K9, K10—GNDCore ground (eDRAM, I/O ground, thermal ground)
VCC18C7, C9, D4, E12, F12, K13, M11—PWRAll 1.8V I/O power:
1.8V power supply for all I/O pins (RESETZ, PARKZ, LED_SEL, CMP_OUT, GPIO, IIC1, TSTPT, and JTAG) except the host or parallel interface and the SPI flash interface.
VCC_INTFM3, M7, N3, N7—PWRHost or parallel interface I/O power: 1.8V to 3.3V (Includes IIC0, PDATA, video syncs, and HOST_IRQ pins)
VCC_FLSHD11—PWRFlash interface I/O power: 1.8V to 3.3V
(Dedicated SPI0 power pin)
VDD_PLLMH2—PWRMCG PLL (primary clock generator phase lock loop) 1.1V power
VSS_PLLMG3—RTNMCG PLL return
VDD_PLLDJ2—PWRDCG PLL (DMD clock generator phase lock loop) 1.1V power
VSS_PLLDH3—RTNDCG PLL return
Table 4-9 I/O Type Subscript Definition
I/OSUPPLY REFERENCEESD STRUCTURE
SUBSCRIPTDESCRIPTION
11.8V LVCMOS I/O buffer with 8mA driveVCC18ESD diode to GND and supply rail
21.8V LVCMOS I/O buffer with 4mA driveVCC18ESD diode to GND and supply rail
31.8V LVCMOS I/O buffer with 24mA driveVCC18ESD diode to GND and supply rail
41.8V SubLVDS output with 4-mA driveVCC18ESD diode to GND and supply rail
51.8V, 2.5V, 3.3V LVCMOS with 4mA driveVCC_INTFESD diode to GND and supply rail
61.8V LVCMOS inputVCC18ESD diode to GND and supply rail
71.8V, 2.5-V, 3.3V I2C with 3mA driveVCC_INTFESD diode to GND and supply rail
81.8V I2C with 3mA driveVCC18ESD diode to GND and supply rail
91.8V, 2.5V, 3.3V LVCMOS with 8mA driveVCC_INTFESD diode to GND and supply rail
10Reserved
111.8V, 2.5V, 3.3V LVCMOS inputVCC_INTFESD diode to GND and supply rail
121.8V, 2.5V, 3.3V LVCMOS inputVCC_FLSHESD diode to GND and supply rail
131.8V, 2.5V, 3.3V LVCMOS with 8mA driveVCC_FLSHESD diode to GND and supply rail