The ADS1282-SP is fabricated in the Texas Instruments high-performance analog 130-nm BiCMOS process (HPA07) with a back-end-of-line (BEOL) stack consisting of X levels of standard thickness aluminum metal on a Y-µm pitch, and a fourth level of thick aluminum. The total stack height from the surface of the passivation to the silicon surface is 10µm, based on nominal layer thickness as shown in Figure 4-2. No polyimide or other coating was present so the uppermost layer was the nitride passivation layer (PON). Accounting for energy loss through the 1-mil thick Aramica (Kevlar®) beam port window, the 40mm air gap, and the BEOL stack over the ADS1282-SP, the effective LET (LET_eff) at the surface of the substrate and the depth and ion range was determined with the custom RADsim-IONS application (custom tool developed at Texas Instruments based on SRIM 2013 [9]) simulations for the two primary ions used for the experiments. The results are shown in Table 4-1. The stack was modeled as a homogeneous layer of silicon dioxide.

Generalized cross-section (left) of the HPA07 technology BEOL stack on the ADS1282-SP. GUI of RADsim-IONS application (right) used to determine key ion parameters: LET_eff, depth, and range for a given ion type, energy, and stack. LET_eff has been adjusted to account for beam degraders inserted into the beam line.